Backhean Tiv

Array ( [id] => 8143731 [patent_doc_number] => 20120096412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-19 [patent_title] => 'Method and System for Forming High Accuracy Patterns Using Charged Particle Beam Lithography' [patent_app_type] => utility [patent_app_number] => 13/168954 [patent_app_country] => US [patent_app_date] => 2011-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11088 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20120096412.pdf [firstpage_image] =>[orig_patent_app_number] => 13168954 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9187248 [patent_doc_number] => 08627249 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-01-07 [patent_title] => 'Method and system for generating design constraints' [patent_app_type] => utility [patent_app_number] => 13/159085 [patent_app_country] => US [patent_app_date] => 2011-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7262 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13159085 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9381382 [patent_doc_number] => 20140084863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-27 [patent_title] => 'POWER RECEIVING DEVICE, VEHICLE, AND CONTACTLESS POWER FEEDING SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/119591 [patent_app_country] => US [patent_app_date] => 2011-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8236 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14119591 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11637161 [patent_doc_number] => 09659136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-23 [patent_title] => 'Suspect logical region synthesis from device design and test information' [patent_app_type] => utility [patent_app_number] => 13/150964 [patent_app_country] => US [patent_app_date] => 2011-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 26 [patent_no_of_words] => 15072 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13150964 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10100525 [patent_doc_number] => 09136847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-15 [patent_title] => 'Signal transmitting-receiving control circuit and secondary battery protection circuit' [patent_app_type] => utility [patent_app_number] => 13/635402 [patent_app_country] => US [patent_app_date] => 2011-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 10863 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13635402 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8681392 [patent_doc_number] => 20130049676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-28 [patent_title] => 'QUICK CHARGING DEVICE AND MOBILE CHARGING APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/579082 [patent_app_country] => US [patent_app_date] => 2011-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4629 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13579082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10053960 [patent_doc_number] => 09093847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-28 [patent_title] => 'Temperature controlled parallel balancing' [patent_app_type] => utility [patent_app_number] => 13/578169 [patent_app_country] => US [patent_app_date] => 2011-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6080 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13578169 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8604281 [patent_doc_number] => 20130009593 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-10 [patent_title] => 'CHARGER AND CHARGING APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/580845 [patent_app_country] => US [patent_app_date] => 2011-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7868 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13580845 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6131623 [patent_doc_number] => 20110088006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-14 [patent_title] => 'METHOD FOR LAYOUT VERIFICATION OF SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/970499 [patent_app_country] => US [patent_app_date] => 2010-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 10584 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20110088006.pdf [firstpage_image] =>[orig_patent_app_number] => 12970499 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10834854 [patent_doc_number] => 08863049 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-10-14 [patent_title] => 'Constraining traces in formal verification' [patent_app_type] => utility [patent_app_number] => 12/961389 [patent_app_country] => US [patent_app_date] => 2010-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5528 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12961389 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9853152 [patent_doc_number] => 08954901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-10 [patent_title] => 'Parameter variation improvement' [patent_app_type] => utility [patent_app_number] => 12/958979 [patent_app_country] => US [patent_app_date] => 2010-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5365 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12958979 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8935829 [patent_doc_number] => 08495551 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-23 [patent_title] => 'Shaping ports in integrated circuit design' [patent_app_type] => utility [patent_app_number] => 12/946179 [patent_app_country] => US [patent_app_date] => 2010-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 5825 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12946179 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9392533 [patent_doc_number] => 08689158 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-01 [patent_title] => 'System and method for performing static timing analysis in the presence of correlations between asserted arrival times' [patent_app_type] => utility [patent_app_number] => 12/944059 [patent_app_country] => US [patent_app_date] => 2010-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5383 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12944059 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10533973 [patent_doc_number] => 09259590 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-16 [patent_title] => 'Tube-structured battery to be inserted into living body' [patent_app_type] => utility [patent_app_number] => 13/635244 [patent_app_country] => US [patent_app_date] => 2010-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 181 [patent_figures_cnt] => 181 [patent_no_of_words] => 61631 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13635244 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9940918 [patent_doc_number] => 08990751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-24 [patent_title] => 'Computer system and method of preparing a layout' [patent_app_type] => utility [patent_app_number] => 12/913949 [patent_app_country] => US [patent_app_date] => 2010-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4587 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12913949 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8176969 [patent_doc_number] => 20120110531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'DEFECT AND YIELD PREDICTION FOR SEGMENTS OF AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/914849 [patent_app_country] => US [patent_app_date] => 2010-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4554 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20120110531.pdf [firstpage_image] =>[orig_patent_app_number] => 12914849 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8849434 [patent_doc_number] => 08458634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-04 [patent_title] => 'Latch clustering with proximity to local clock buffers' [patent_app_type] => utility [patent_app_number] => 12/912919 [patent_app_country] => US [patent_app_date] => 2010-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6350 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12912919 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8414775 [patent_doc_number] => 20120242275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-27 [patent_title] => 'LARGE-SCALE OCEAN MOBILE SOLAR POWER GENERATION SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/501272 [patent_app_country] => US [patent_app_date] => 2010-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9948 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13501272 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7658578 [patent_doc_number] => 20110307847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-15 [patent_title] => 'Hybrid system combining TLM simulators and HW accelerators' [patent_app_type] => utility [patent_app_number] => 12/802706 [patent_app_country] => US [patent_app_date] => 2010-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4616 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20110307847.pdf [firstpage_image] =>[orig_patent_app_number] => 12802706 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11252299 [patent_doc_number] => 09477802 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-10-25 [patent_title] => 'Isolating differences between revisions of a circuit design' [patent_app_type] => utility [patent_app_number] => 12/797476 [patent_app_country] => US [patent_app_date] => 2010-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 10029 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12797476 [rel_patent_id] =>[rel_patent_doc_number] =>)