Backhean Tiv

Array ( [id] => 9326341 [patent_doc_number] => 08661378 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-25 [patent_title] => 'Asychronous system analysis' [patent_app_type] => utility [patent_app_number] => 12/570629 [patent_app_country] => US [patent_app_date] => 2009-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4957 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12570629 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6389558 [patent_doc_number] => 20100083206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'Clock signal providing circuit designing method, information processing apparatus and computer-readable information recording medium' [patent_app_type] => utility [patent_app_number] => 12/585959 [patent_app_country] => US [patent_app_date] => 2009-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 13992 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20100083206.pdf [firstpage_image] =>[orig_patent_app_number] => 12585959 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6527380 [patent_doc_number] => 20100262409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'BLENDED MODEL INTERPOLATION' [patent_app_type] => utility [patent_app_number] => 12/420879 [patent_app_country] => US [patent_app_date] => 2009-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5305 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20100262409.pdf [firstpage_image] =>[orig_patent_app_number] => 12420879 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8899599 [patent_doc_number] => 08479133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-02 [patent_title] => 'Method of and circuit for implementing a filter in an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/418979 [patent_app_country] => US [patent_app_date] => 2009-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 11011 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12418979 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8285831 [patent_doc_number] => 08219950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-10 [patent_title] => 'Propagation delay time balancing in chained inverting devices' [patent_app_type] => utility [patent_app_number] => 12/382689 [patent_app_country] => US [patent_app_date] => 2009-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5045 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12382689 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5476106 [patent_doc_number] => 20090249272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-01 [patent_title] => 'STATISTICAL TIMING ANALYZER AND STATISTICAL TIMING ANALYSIS METHOD' [patent_app_type] => utility [patent_app_number] => 12/400819 [patent_app_country] => US [patent_app_date] => 2009-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8647 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0249/20090249272.pdf [firstpage_image] =>[orig_patent_app_number] => 12400819 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6652452 [patent_doc_number] => 20100229143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-09 [patent_title] => 'DETECTION AND REMOVAL OF HAZARDS DURING OPTIMIZATION OF LOGIC CIRCUITS' [patent_app_type] => utility [patent_app_number] => 12/399119 [patent_app_country] => US [patent_app_date] => 2009-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8978 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20100229143.pdf [firstpage_image] =>[orig_patent_app_number] => 12399119 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8235661 [patent_doc_number] => 08201123 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-06-12 [patent_title] => 'Automatic input/output timing adjustment flow for programmable integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/394949 [patent_app_country] => US [patent_app_date] => 2009-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 7573 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/201/08201123.pdf [firstpage_image] =>[orig_patent_app_number] => 12394949 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6535272 [patent_doc_number] => 20100218150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-26 [patent_title] => 'Logic Design Verification Techniques for Liveness Checking' [patent_app_type] => utility [patent_app_number] => 12/393779 [patent_app_country] => US [patent_app_date] => 2009-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10067 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20100218150.pdf [firstpage_image] =>[orig_patent_app_number] => 12393779 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5514947 [patent_doc_number] => 20090215254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'Design support system,computer readable medium, semiconductor device designing method and semiconductor device manufacturing method' [patent_app_type] => utility [patent_app_number] => 12/379169 [patent_app_country] => US [patent_app_date] => 2009-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7159 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20090215254.pdf [firstpage_image] =>[orig_patent_app_number] => 12379169 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8001369 [patent_doc_number] => 08082532 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-12-20 [patent_title] => 'Placing complex function blocks on a programmable integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/364719 [patent_app_country] => US [patent_app_date] => 2009-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 11936 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/082/08082532.pdf [firstpage_image] =>[orig_patent_app_number] => 12364719 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6314085 [patent_doc_number] => 20100194779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'METHOD AND SYSTEM FOR SIZING POLYGONS IN AN INTEGRATED CIRCUIT (IC) LAYOUT' [patent_app_type] => utility [patent_app_number] => 12/363159 [patent_app_country] => US [patent_app_date] => 2009-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6158 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20100194779.pdf [firstpage_image] =>[orig_patent_app_number] => 12363159 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5557381 [patent_doc_number] => 20090268958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-29 [patent_title] => ' DUAL-PURPOSE PERTURBATION ENGINE FOR AUTOMATICALLY PROCESSING PATTERN-CLIP-BASED MANUFACTURING HOTSPOTS' [patent_app_type] => utility [patent_app_number] => 12/275887 [patent_app_country] => US [patent_app_date] => 2008-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6237 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20090268958.pdf [firstpage_image] =>[orig_patent_app_number] => 12275887 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5523297 [patent_doc_number] => 20090031278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'ARCHITECTURAL PHYSICAL SYNTHESIS' [patent_app_type] => utility [patent_app_number] => 12/177869 [patent_app_country] => US [patent_app_date] => 2008-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12901 [patent_no_of_claims] => 70 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20090031278.pdf [firstpage_image] =>[orig_patent_app_number] => 12177869 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8645778 [patent_doc_number] => 08370776 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-02-05 [patent_title] => 'Method and apparatus for compiling intellectual property systems design cores using an incremental compile design flow' [patent_app_type] => utility [patent_app_number] => 12/157809 [patent_app_country] => US [patent_app_date] => 2008-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6049 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12157809 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9630137 [patent_doc_number] => 08799831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-05 [patent_title] => 'Inline defect analysis for sampling and SPC' [patent_app_type] => utility [patent_app_number] => 12/154629 [patent_app_country] => US [patent_app_date] => 2008-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7205 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12154629 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9326344 [patent_doc_number] => 08661381 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-02-25 [patent_title] => 'Method and apparatus for performing optimization using Don\'t Care states' [patent_app_type] => utility [patent_app_number] => 12/152499 [patent_app_country] => US [patent_app_date] => 2008-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 7645 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12152499 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5560172 [patent_doc_number] => 20090271749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-29 [patent_title] => 'PATTERN-CLIP-BASED HOTSPOT DATABASE SYSTEM FOR LAYOUT VERIFICATION' [patent_app_type] => utility [patent_app_number] => 12/109118 [patent_app_country] => US [patent_app_date] => 2008-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6242 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20090271749.pdf [firstpage_image] =>[orig_patent_app_number] => 12109118 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5497506 [patent_doc_number] => 20090265534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-22 [patent_title] => 'Fairness, Performance, and Livelock Assessment Using a Loop Manager With Comparative Parallel Looping' [patent_app_type] => utility [patent_app_number] => 12/104638 [patent_app_country] => US [patent_app_date] => 2008-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5910 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20090265534.pdf [firstpage_image] =>[orig_patent_app_number] => 12104638 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7982875 [patent_doc_number] => 08074196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-06 [patent_title] => 'Integrated circuit design support apparatus, integrated circuit design support method, integrated circuit design support program, and recording medium with said program recorded therein' [patent_app_type] => utility [patent_app_number] => 12/103958 [patent_app_country] => US [patent_app_date] => 2008-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 24 [patent_no_of_words] => 5930 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/074/08074196.pdf [firstpage_image] =>[orig_patent_app_number] => 12103958 [rel_patent_id] =>[rel_patent_doc_number] =>)