
Backhean Tiv
Examiner (ID: 5442, Phone: (571)272-5654 , Office: P/2451 )
| Most Active Art Unit | 2459 |
| Art Unit(s) | 2459, 2451, 2151 |
| Total Applications | 1157 |
| Issued Applications | 842 |
| Pending Applications | 79 |
| Abandoned Applications | 250 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5418271
[patent_doc_number] => 20090044158
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-02-12
[patent_title] => 'METHOD, AND EXTENSIONS, TO COUPLE SUBSTRATE EFFECTS AND COMPACT MODEL CIRCUIT SIMULATION FOR EFFICIENT SIMULATION OF SEMICONDUCTOR DEVICES AND CIRCUIT'
[patent_app_type] => utility
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[patent_app_date] => 2008-04-11
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/101808 | METHOD, AND EXTENSIONS, TO COUPLE SUBSTRATE EFFECTS AND COMPACT MODEL CIRCUIT SIMULATION FOR EFFICIENT SIMULATION OF SEMICONDUCTOR DEVICES AND CIRCUIT | Apr 10, 2008 | Abandoned |
Array
(
[id] => 4665597
[patent_doc_number] => 20080256504
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[patent_kind] => A1
[patent_issue_date] => 2008-10-16
[patent_title] => 'MASK PATTERN DESIGN METHOD AND SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR DESIGN PROGRAM'
[patent_app_type] => utility
[patent_app_number] => 12/099928
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[patent_app_date] => 2008-04-09
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/099928 | Mask pattern design method and semiconductor manufacturing method and semiconductor design program | Apr 8, 2008 | Issued |
Array
(
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[patent_kind] => A1
[patent_issue_date] => 2008-10-02
[patent_title] => 'CIRCUIT DESIGN VERIFICATION SYSTEM, METHOD AND MEDIUM'
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Array
(
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[patent_issue_date] => 2008-10-30
[patent_title] => 'Method for processing pattern data and method for manufacturing electronic device'
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Array
(
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[patent_title] => 'Method and apparatus for performing simultaneous register retiming and combinational resynthesis during physical synthesis'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/075488 | Method and apparatus for performing simultaneous register retiming and combinational resynthesis during physical synthesis | Mar 11, 2008 | Issued |
Array
(
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[patent_title] => 'Delay analysis support apparatus, delay analysis support method and computer product'
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Array
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[patent_title] => 'Multiple derating factor sets for delay calculation and library generation in multi-corner STA sign-off flow'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/072478 | Multiple derating factor sets for delay calculation and library generation in multi-corner STA sign-off flow | Feb 25, 2008 | Issued |
Array
(
[id] => 4678398
[patent_doc_number] => 20080216029
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[patent_issue_date] => 2008-09-04
[patent_title] => 'METHOD AND SYSTEM FOR PERFORMING TARGET ENLARGEMENT IN THE PRESENCE OF CONSTRAINTS'
[patent_app_type] => utility
[patent_app_number] => 12/036093
[patent_app_country] => US
[patent_app_date] => 2008-02-22
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[firstpage_image] =>[orig_patent_app_number] => 12036093
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/036093 | Method and system for performing target enlargement in the presence of constraints | Feb 21, 2008 | Issued |
Array
(
[id] => 9326343
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[patent_issue_date] => 2014-02-25
[patent_title] => 'Method and apparatus for performing parallel synthesis on a field programmable gate array'
[patent_app_type] => utility
[patent_app_number] => 12/070478
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/070478 | Method and apparatus for performing parallel synthesis on a field programmable gate array | Feb 18, 2008 | Issued |
Array
(
[id] => 8120431
[patent_doc_number] => 08161439
[patent_country] => US
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[patent_issue_date] => 2012-04-17
[patent_title] => 'Method and apparatus for processing assertions in assertion-based verification of a logic design'
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Array
(
[id] => 5381537
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[patent_title] => 'CLOCK POWER MINIMIZATION WITH REGULAR PHYSICAL PLACEMENT OF CLOCK REPEATER COMPONENTS'
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Array
(
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Array
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Array
(
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Array
(
[id] => 9579029
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/955689 | Method and system for automatically accessing internal signals or ports in a design hierarchy | Dec 12, 2007 | Issued |
Array
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Array
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Array
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Array
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