Search

Backhean Tiv

Examiner (ID: 5442, Phone: (571)272-5654 , Office: P/2451 )

Most Active Art Unit
2459
Art Unit(s)
2459, 2451, 2151
Total Applications
1157
Issued Applications
842
Pending Applications
79
Abandoned Applications
250

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5418271 [patent_doc_number] => 20090044158 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-12 [patent_title] => 'METHOD, AND EXTENSIONS, TO COUPLE SUBSTRATE EFFECTS AND COMPACT MODEL CIRCUIT SIMULATION FOR EFFICIENT SIMULATION OF SEMICONDUCTOR DEVICES AND CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/101808 [patent_app_country] => US [patent_app_date] => 2008-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2227 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20090044158.pdf [firstpage_image] =>[orig_patent_app_number] => 12101808 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/101808
METHOD, AND EXTENSIONS, TO COUPLE SUBSTRATE EFFECTS AND COMPACT MODEL CIRCUIT SIMULATION FOR EFFICIENT SIMULATION OF SEMICONDUCTOR DEVICES AND CIRCUIT Apr 10, 2008 Abandoned
Array ( [id] => 4665597 [patent_doc_number] => 20080256504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-16 [patent_title] => 'MASK PATTERN DESIGN METHOD AND SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR DESIGN PROGRAM' [patent_app_type] => utility [patent_app_number] => 12/099928 [patent_app_country] => US [patent_app_date] => 2008-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5451 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20080256504.pdf [firstpage_image] =>[orig_patent_app_number] => 12099928 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/099928
Mask pattern design method and semiconductor manufacturing method and semiconductor design program Apr 8, 2008 Issued
Array ( [id] => 4722870 [patent_doc_number] => 20080244484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'CIRCUIT DESIGN VERIFICATION SYSTEM, METHOD AND MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/058136 [patent_app_country] => US [patent_app_date] => 2008-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4744 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20080244484.pdf [firstpage_image] =>[orig_patent_app_number] => 12058136 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/058136
CIRCUIT DESIGN VERIFICATION SYSTEM, METHOD AND MEDIUM Mar 27, 2008 Abandoned
Array ( [id] => 4862665 [patent_doc_number] => 20080270970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'Method for processing pattern data and method for manufacturing electronic device' [patent_app_type] => utility [patent_app_number] => 12/078178 [patent_app_country] => US [patent_app_date] => 2008-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9449 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20080270970.pdf [firstpage_image] =>[orig_patent_app_number] => 12078178 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/078178
Method for processing pattern data and method for manufacturing electronic device Mar 26, 2008 Abandoned
Array ( [id] => 8461010 [patent_doc_number] => 08296696 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-10-23 [patent_title] => 'Method and apparatus for performing simultaneous register retiming and combinational resynthesis during physical synthesis' [patent_app_type] => utility [patent_app_number] => 12/075488 [patent_app_country] => US [patent_app_date] => 2008-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 8994 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12075488 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/075488
Method and apparatus for performing simultaneous register retiming and combinational resynthesis during physical synthesis Mar 11, 2008 Issued
Array ( [id] => 4722878 [patent_doc_number] => 20080244487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'Delay analysis support apparatus, delay analysis support method and computer product' [patent_app_type] => utility [patent_app_number] => 12/073038 [patent_app_country] => US [patent_app_date] => 2008-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6221 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20080244487.pdf [firstpage_image] =>[orig_patent_app_number] => 12073038 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/073038
Delay analysis support apparatus, delay analysis support method and computer product Feb 27, 2008 Issued
Array ( [id] => 5516919 [patent_doc_number] => 20090217226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'Multiple derating factor sets for delay calculation and library generation in multi-corner STA sign-off flow' [patent_app_type] => utility [patent_app_number] => 12/072478 [patent_app_country] => US [patent_app_date] => 2008-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4907 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20090217226.pdf [firstpage_image] =>[orig_patent_app_number] => 12072478 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/072478
Multiple derating factor sets for delay calculation and library generation in multi-corner STA sign-off flow Feb 25, 2008 Issued
Array ( [id] => 4678398 [patent_doc_number] => 20080216029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'METHOD AND SYSTEM FOR PERFORMING TARGET ENLARGEMENT IN THE PRESENCE OF CONSTRAINTS' [patent_app_type] => utility [patent_app_number] => 12/036093 [patent_app_country] => US [patent_app_date] => 2008-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8676 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20080216029.pdf [firstpage_image] =>[orig_patent_app_number] => 12036093 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/036093
Method and system for performing target enlargement in the presence of constraints Feb 21, 2008 Issued
Array ( [id] => 9326343 [patent_doc_number] => 08661380 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-02-25 [patent_title] => 'Method and apparatus for performing parallel synthesis on a field programmable gate array' [patent_app_type] => utility [patent_app_number] => 12/070478 [patent_app_country] => US [patent_app_date] => 2008-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 7715 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12070478 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/070478
Method and apparatus for performing parallel synthesis on a field programmable gate array Feb 18, 2008 Issued
Array ( [id] => 8120431 [patent_doc_number] => 08161439 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-17 [patent_title] => 'Method and apparatus for processing assertions in assertion-based verification of a logic design' [patent_app_type] => utility [patent_app_number] => 12/028909 [patent_app_country] => US [patent_app_date] => 2008-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6286 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/161/08161439.pdf [firstpage_image] =>[orig_patent_app_number] => 12028909 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/028909
Method and apparatus for processing assertions in assertion-based verification of a logic design Feb 10, 2008 Issued
Array ( [id] => 5381537 [patent_doc_number] => 20090193376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-30 [patent_title] => 'CLOCK POWER MINIMIZATION WITH REGULAR PHYSICAL PLACEMENT OF CLOCK REPEATER COMPONENTS' [patent_app_type] => utility [patent_app_number] => 12/022849 [patent_app_country] => US [patent_app_date] => 2008-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5105 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20090193376.pdf [firstpage_image] =>[orig_patent_app_number] => 12022849 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/022849
Clock power minimization with regular physical placement of clock repeater components Jan 29, 2008 Issued
Array ( [id] => 4722877 [patent_doc_number] => 20080244486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'INTEGRATED CIRCUIT GENERATING DEVICE, METHOD THEREFOR, AND PROGRAM' [patent_app_type] => utility [patent_app_number] => 12/019249 [patent_app_country] => US [patent_app_date] => 2008-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 12158 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20080244486.pdf [firstpage_image] =>[orig_patent_app_number] => 12019249 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/019249
INTEGRATED CIRCUIT GENERATING DEVICE, METHOD THEREFOR, AND PROGRAM Jan 23, 2008 Abandoned
Array ( [id] => 5356533 [patent_doc_number] => 20090187877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-23 [patent_title] => 'MULTI-PASS, CONSTRAINED PHASE ASSIGNMENT FOR ALTERNATING PHASE-SHIFT LITHOGRAPHY' [patent_app_type] => utility [patent_app_number] => 12/017699 [patent_app_country] => US [patent_app_date] => 2008-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6277 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20090187877.pdf [firstpage_image] =>[orig_patent_app_number] => 12017699 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/017699
MULTI-PASS, CONSTRAINED PHASE ASSIGNMENT FOR ALTERNATING PHASE-SHIFT LITHOGRAPHY Jan 21, 2008 Abandoned
Array ( [id] => 4700289 [patent_doc_number] => 20080222473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'TEST PATTERN GENERATING DEVICE AND TEST PATTERN GENERATING METHOD' [patent_app_type] => utility [patent_app_number] => 12/014119 [patent_app_country] => US [patent_app_date] => 2008-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7995 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20080222473.pdf [firstpage_image] =>[orig_patent_app_number] => 12014119 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/014119
TEST PATTERN GENERATING DEVICE AND TEST PATTERN GENERATING METHOD Jan 14, 2008 Abandoned
Array ( [id] => 9579029 [patent_doc_number] => 08769467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-01 [patent_title] => 'Method and system for utilizing hard and preferred rules for C-routing of electronic designs' [patent_app_type] => utility [patent_app_number] => 11/964639 [patent_app_country] => US [patent_app_date] => 2007-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 7742 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11964639 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/964639
Method and system for utilizing hard and preferred rules for C-routing of electronic designs Dec 25, 2007 Issued
Array ( [id] => 5548348 [patent_doc_number] => 20090158225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'METHOD AND SYSTEM FOR AUTOMATICALLY ACCESSING INTERNAL SIGNALS OR PORTS IN A DESIGN HIERARCHY' [patent_app_type] => utility [patent_app_number] => 11/955689 [patent_app_country] => US [patent_app_date] => 2007-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3923 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20090158225.pdf [firstpage_image] =>[orig_patent_app_number] => 11955689 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/955689
Method and system for automatically accessing internal signals or ports in a design hierarchy Dec 12, 2007 Issued
Array ( [id] => 5424388 [patent_doc_number] => 20090150844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-11 [patent_title] => 'CRITICAL PATH SELECTION FOR AT-SPEED TEST' [patent_app_type] => utility [patent_app_number] => 11/954138 [patent_app_country] => US [patent_app_date] => 2007-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2863 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20090150844.pdf [firstpage_image] =>[orig_patent_app_number] => 11954138 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/954138
CRITICAL PATH SELECTION FOR AT-SPEED TEST Dec 10, 2007 Abandoned
Array ( [id] => 4574193 [patent_doc_number] => 07962886 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-06-14 [patent_title] => 'Method and system for generating design constraints' [patent_app_type] => utility [patent_app_number] => 11/952798 [patent_app_country] => US [patent_app_date] => 2007-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7229 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/962/07962886.pdf [firstpage_image] =>[orig_patent_app_number] => 11952798 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/952798
Method and system for generating design constraints Dec 6, 2007 Issued
Array ( [id] => 4869147 [patent_doc_number] => 20080148198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'HOTSPOT TOTALIZATION METHOD, PATTERN CORRECTION METHOD, AND PROGRAM' [patent_app_type] => utility [patent_app_number] => 11/951868 [patent_app_country] => US [patent_app_date] => 2007-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4436 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20080148198.pdf [firstpage_image] =>[orig_patent_app_number] => 11951868 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/951868
HOTSPOT TOTALIZATION METHOD, PATTERN CORRECTION METHOD, AND PROGRAM Dec 5, 2007 Abandoned
Array ( [id] => 5577324 [patent_doc_number] => 20090144686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-04 [patent_title] => 'METHOD AND APPARATUS FOR MONITORING MARGINAL LAYOUT DESIGN RULES' [patent_app_type] => utility [patent_app_number] => 11/948218 [patent_app_country] => US [patent_app_date] => 2007-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6552 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20090144686.pdf [firstpage_image] =>[orig_patent_app_number] => 11948218 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/948218
METHOD AND APPARATUS FOR MONITORING MARGINAL LAYOUT DESIGN RULES Nov 29, 2007 Abandoned
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