
Backhean Tiv
Examiner (ID: 5442, Phone: (571)272-5654 , Office: P/2451 )
| Most Active Art Unit | 2459 |
| Art Unit(s) | 2459, 2451, 2151 |
| Total Applications | 1157 |
| Issued Applications | 842 |
| Pending Applications | 79 |
| Abandoned Applications | 250 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5444613
[patent_doc_number] => 20090045839
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[patent_kind] => A1
[patent_issue_date] => 2009-02-19
[patent_title] => 'ASIC LOGIC LIBRARY OF FLEXIBLE LOGIC BLOCKS AND METHOD TO ENABLE ENGINEERING CHANGE'
[patent_app_type] => utility
[patent_app_number] => 11/876263
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[patent_app_date] => 2007-10-22
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/876263 | ASIC LOGIC LIBRARY OF FLEXIBLE LOGIC BLOCKS AND METHOD TO ENABLE ENGINEERING CHANGE | Oct 21, 2007 | Abandoned |
Array
(
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[patent_doc_number] => 20080059923
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[patent_kind] => A1
[patent_issue_date] => 2008-03-06
[patent_title] => 'LSI POWER CONSUMPTION CALCULATION METHOD AND CALCULATION PROGRAM'
[patent_app_type] => utility
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Array
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[patent_issue_date] => 2008-03-20
[patent_title] => 'Wordline Booster Design Structure and Method of Operating a Wordline Booster Circuit'
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[patent_app_number] => 11/847759
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Array
(
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[patent_title] => 'Modeling silicon-on-insulator stress effects'
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Array
(
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[patent_title] => 'Secure Yield-aware Design Flow with Annotated Design Libraries'
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Array
(
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Array
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Array
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Array
(
[id] => 4889160
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[patent_title] => '3-Dimensional Device Design Layout'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/833119 | 3-dimensional device design layout | Aug 1, 2007 | Issued |
Array
(
[id] => 4911487
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[patent_issue_date] => 2008-01-24
[patent_title] => 'SYSTEM AND METHOD FOR IMPROVING MASK TAPE-OUT PROCESS'
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Array
(
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Array
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Array
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Array
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