Search

Backhean Tiv

Examiner (ID: 5442, Phone: (571)272-5654 , Office: P/2451 )

Most Active Art Unit
2459
Art Unit(s)
2459, 2451, 2151
Total Applications
1157
Issued Applications
842
Pending Applications
79
Abandoned Applications
250

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5444613 [patent_doc_number] => 20090045839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-19 [patent_title] => 'ASIC LOGIC LIBRARY OF FLEXIBLE LOGIC BLOCKS AND METHOD TO ENABLE ENGINEERING CHANGE' [patent_app_type] => utility [patent_app_number] => 11/876263 [patent_app_country] => US [patent_app_date] => 2007-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3960 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20090045839.pdf [firstpage_image] =>[orig_patent_app_number] => 11876263 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/876263
ASIC LOGIC LIBRARY OF FLEXIBLE LOGIC BLOCKS AND METHOD TO ENABLE ENGINEERING CHANGE Oct 21, 2007 Abandoned
Array ( [id] => 4774261 [patent_doc_number] => 20080059923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'LSI POWER CONSUMPTION CALCULATION METHOD AND CALCULATION PROGRAM' [patent_app_type] => utility [patent_app_number] => 11/849999 [patent_app_country] => US [patent_app_date] => 2007-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8162 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20080059923.pdf [firstpage_image] =>[orig_patent_app_number] => 11849999 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/849999
LSI POWER CONSUMPTION CALCULATION METHOD AND CALCULATION PROGRAM Sep 3, 2007 Abandoned
Array ( [id] => 4920588 [patent_doc_number] => 20080068902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'Wordline Booster Design Structure and Method of Operating a Wordline Booster Circuit' [patent_app_type] => utility [patent_app_number] => 11/847759 [patent_app_country] => US [patent_app_date] => 2007-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5178 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20080068902.pdf [firstpage_image] =>[orig_patent_app_number] => 11847759 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/847759
Wordline booster design structure and method of operating a wordine booster circuit Aug 29, 2007 Issued
Array ( [id] => 4470368 [patent_doc_number] => 07882452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-01 [patent_title] => 'Modeling silicon-on-insulator stress effects' [patent_app_type] => utility [patent_app_number] => 11/847999 [patent_app_country] => US [patent_app_date] => 2007-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2431 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/882/07882452.pdf [firstpage_image] =>[orig_patent_app_number] => 11847999 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/847999
Modeling silicon-on-insulator stress effects Aug 29, 2007 Issued
Array ( [id] => 5339318 [patent_doc_number] => 20090055782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-26 [patent_title] => 'Secure Yield-aware Design Flow with Annotated Design Libraries' [patent_app_type] => utility [patent_app_number] => 11/841509 [patent_app_country] => US [patent_app_date] => 2007-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3037 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20090055782.pdf [firstpage_image] =>[orig_patent_app_number] => 11841509 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/841509
Secure Yield-aware Design Flow with Annotated Design Libraries Aug 19, 2007 Abandoned
Array ( [id] => 4780901 [patent_doc_number] => 20080288900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-20 [patent_title] => 'DETERMINATION OF SINGLE-FIX RECTIFICATION FUNCTION' [patent_app_type] => utility [patent_app_number] => 11/841079 [patent_app_country] => US [patent_app_date] => 2007-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5557 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20080288900.pdf [firstpage_image] =>[orig_patent_app_number] => 11841079 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/841079
Determination of single-fix rectification function Aug 19, 2007 Issued
Array ( [id] => 5298375 [patent_doc_number] => 20090013301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-08 [patent_title] => 'Hardware definition language generation for frame-based processing' [patent_app_type] => utility [patent_app_number] => 11/842099 [patent_app_country] => US [patent_app_date] => 2007-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11473 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20090013301.pdf [firstpage_image] =>[orig_patent_app_number] => 11842099 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/842099
Hardware definition language generation for frame-based processing Aug 19, 2007 Issued
Array ( [id] => 5444610 [patent_doc_number] => 20090045836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-19 [patent_title] => 'ASIC LOGIC LIBRARY OF FLEXIBLE LOGIC BLOCKS AND METHOD TO ENABLE ENGINEERING CHANGE' [patent_app_type] => utility [patent_app_number] => 11/838929 [patent_app_country] => US [patent_app_date] => 2007-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3083 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20090045836.pdf [firstpage_image] =>[orig_patent_app_number] => 11838929 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/838929
ASIC LOGIC LIBRARY OF FLEXIBLE LOGIC BLOCKS AND METHOD TO ENABLE ENGINEERING CHANGE Aug 14, 2007 Abandoned
Array ( [id] => 4889160 [patent_doc_number] => 20080263492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => '3-Dimensional Device Design Layout' [patent_app_type] => utility [patent_app_number] => 11/833119 [patent_app_country] => US [patent_app_date] => 2007-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4004 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20080263492.pdf [firstpage_image] =>[orig_patent_app_number] => 11833119 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/833119
3-dimensional device design layout Aug 1, 2007 Issued
Array ( [id] => 4911487 [patent_doc_number] => 20080022254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-24 [patent_title] => 'SYSTEM AND METHOD FOR IMPROVING MASK TAPE-OUT PROCESS' [patent_app_type] => utility [patent_app_number] => 11/697800 [patent_app_country] => US [patent_app_date] => 2007-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3006 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20080022254.pdf [firstpage_image] =>[orig_patent_app_number] => 11697800 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/697800
SYSTEM AND METHOD FOR IMPROVING MASK TAPE-OUT PROCESS Apr 8, 2007 Abandoned
Array ( [id] => 4684150 [patent_doc_number] => 20080250376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-09 [patent_title] => 'Integrating a boolean SAT solver into a router' [patent_app_type] => utility [patent_app_number] => 11/732848 [patent_app_country] => US [patent_app_date] => 2007-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6408 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20080250376.pdf [firstpage_image] =>[orig_patent_app_number] => 11732848 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/732848
Integrating a boolean SAT solver into a router Apr 3, 2007 Issued
Array ( [id] => 7525083 [patent_doc_number] => 08028253 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-27 [patent_title] => 'Method and apparatus for determining mask layouts for a multiple patterning process' [patent_app_type] => utility [patent_app_number] => 11/732268 [patent_app_country] => US [patent_app_date] => 2007-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3026 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/028/08028253.pdf [firstpage_image] =>[orig_patent_app_number] => 11732268 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/732268
Method and apparatus for determining mask layouts for a multiple patterning process Apr 1, 2007 Issued
Array ( [id] => 4722927 [patent_doc_number] => 20080244501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'METHOD FOR READING INFORMATION FROM A HIERARCHICAL DESIGN' [patent_app_type] => utility [patent_app_number] => 11/695461 [patent_app_country] => US [patent_app_date] => 2007-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1774 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20080244501.pdf [firstpage_image] =>[orig_patent_app_number] => 11695461 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/695461
METHOD FOR READING INFORMATION FROM A HIERARCHICAL DESIGN Apr 1, 2007 Abandoned
Array ( [id] => 4722841 [patent_doc_number] => 20080244473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'Modifying Integrated Circuit Designs to Achieve Multiple Operating Frequency Targets' [patent_app_type] => utility [patent_app_number] => 11/693081 [patent_app_country] => US [patent_app_date] => 2007-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4807 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20080244473.pdf [firstpage_image] =>[orig_patent_app_number] => 11693081 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/693081
Modifying integrated circuit designs to achieve multiple operating frequency targets Mar 28, 2007 Issued
Array ( [id] => 4653443 [patent_doc_number] => 20080040700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'Behavioral synthesizer, debugger, writing device and computer aided design system and method' [patent_app_type] => utility [patent_app_number] => 11/727948 [patent_app_country] => US [patent_app_date] => 2007-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8192 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20080040700.pdf [firstpage_image] =>[orig_patent_app_number] => 11727948 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/727948
Behavioral synthesizer, debugger, writing device and computer aided design system and method Mar 28, 2007 Abandoned
Array ( [id] => 4722595 [patent_doc_number] => 20080244347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'Automated Circuit Model Generator' [patent_app_type] => utility [patent_app_number] => 11/692601 [patent_app_country] => US [patent_app_date] => 2007-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4772 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20080244347.pdf [firstpage_image] =>[orig_patent_app_number] => 11692601 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/692601
Automated Circuit Model Generator Mar 27, 2007 Abandoned
Array ( [id] => 5127818 [patent_doc_number] => 20070240089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-11 [patent_title] => 'Apparatus and method for correcting layout pattern data' [patent_app_type] => utility [patent_app_number] => 11/727738 [patent_app_country] => US [patent_app_date] => 2007-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5368 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20070240089.pdf [firstpage_image] =>[orig_patent_app_number] => 11727738 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/727738
Apparatus and method for correcting layout pattern data Mar 27, 2007 Abandoned
Array ( [id] => 5065034 [patent_doc_number] => 20070226676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-27 [patent_title] => 'Calculating method, verification method, verification program and verification system for edge deviation quantity, and semiconductor device manufacturing method' [patent_app_type] => utility [patent_app_number] => 11/727288 [patent_app_country] => US [patent_app_date] => 2007-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9042 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20070226676.pdf [firstpage_image] =>[orig_patent_app_number] => 11727288 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/727288
Calculating method, verification method, verification program and verification system for edge deviation quantity, and semiconductor device manufacturing method Mar 25, 2007 Issued
Array ( [id] => 8461011 [patent_doc_number] => 08296697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-23 [patent_title] => 'Method and apparatus for performing static analysis optimization in a design verification system' [patent_app_type] => utility [patent_app_number] => 11/725288 [patent_app_country] => US [patent_app_date] => 2007-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5473 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11725288 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/725288
Method and apparatus for performing static analysis optimization in a design verification system Mar 18, 2007 Issued
Array ( [id] => 4523251 [patent_doc_number] => 07917881 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-03-29 [patent_title] => 'Timing of a circuit design' [patent_app_type] => utility [patent_app_number] => 11/725188 [patent_app_country] => US [patent_app_date] => 2007-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7175 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/917/07917881.pdf [firstpage_image] =>[orig_patent_app_number] => 11725188 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/725188
Timing of a circuit design Mar 14, 2007 Issued
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