Search

Backhean Tiv

Examiner (ID: 5442, Phone: (571)272-5654 , Office: P/2451 )

Most Active Art Unit
2459
Art Unit(s)
2459, 2451, 2151
Total Applications
1157
Issued Applications
842
Pending Applications
79
Abandoned Applications
250

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8623339 [patent_doc_number] => 08356260 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-15 [patent_title] => 'Method and apparatus for monitoring cross-sectional shape of a pattern formed on a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/673065 [patent_app_country] => US [patent_app_date] => 2007-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 57 [patent_no_of_words] => 25032 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11673065 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/673065
Method and apparatus for monitoring cross-sectional shape of a pattern formed on a semiconductor device Feb 8, 2007 Issued
Array ( [id] => 4550883 [patent_doc_number] => 07926020 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-04-12 [patent_title] => 'Methods for automatically generating assertions' [patent_app_type] => utility [patent_app_number] => 11/672919 [patent_app_country] => US [patent_app_date] => 2007-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2965 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/926/07926020.pdf [firstpage_image] =>[orig_patent_app_number] => 11672919 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/672919
Methods for automatically generating assertions Feb 7, 2007 Issued
Array ( [id] => 4528374 [patent_doc_number] => 07934177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-26 [patent_title] => 'Method and system for a pattern layout split' [patent_app_type] => utility [patent_app_number] => 11/671866 [patent_app_country] => US [patent_app_date] => 2007-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7156 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/934/07934177.pdf [firstpage_image] =>[orig_patent_app_number] => 11671866 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/671866
Method and system for a pattern layout split Feb 5, 2007 Issued
Array ( [id] => 4956649 [patent_doc_number] => 20080189673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-07 [patent_title] => 'PATTERN MATCH BASED OPTICAL PROXIMITY CORRECTION AND VERIFICATION OF INTEGRATED CIRCUIT LAYOUT' [patent_app_type] => utility [patent_app_number] => 11/670975 [patent_app_country] => US [patent_app_date] => 2007-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6168 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20080189673.pdf [firstpage_image] =>[orig_patent_app_number] => 11670975 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/670975
Pattern match based optical proximity correction and verification of integrated circuit layout Feb 2, 2007 Issued
Array ( [id] => 19190 [patent_doc_number] => 07810063 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-10-05 [patent_title] => 'Graphical user interface for prototyping early instance density' [patent_app_type] => utility [patent_app_number] => 11/670366 [patent_app_country] => US [patent_app_date] => 2007-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7546 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/810/07810063.pdf [firstpage_image] =>[orig_patent_app_number] => 11670366 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/670366
Graphical user interface for prototyping early instance density Jan 31, 2007 Issued
Array ( [id] => 38588 [patent_doc_number] => 07788621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-31 [patent_title] => 'Method and apparatus for creating layout model, computer product, and method of manufacturing device' [patent_app_type] => utility [patent_app_number] => 11/698854 [patent_app_country] => US [patent_app_date] => 2007-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7569 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/788/07788621.pdf [firstpage_image] =>[orig_patent_app_number] => 11698854 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/698854
Method and apparatus for creating layout model, computer product, and method of manufacturing device Jan 28, 2007 Issued
Array ( [id] => 38588 [patent_doc_number] => 07788621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-31 [patent_title] => 'Method and apparatus for creating layout model, computer product, and method of manufacturing device' [patent_app_type] => utility [patent_app_number] => 11/698854 [patent_app_country] => US [patent_app_date] => 2007-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7569 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/788/07788621.pdf [firstpage_image] =>[orig_patent_app_number] => 11698854 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/698854
Method and apparatus for creating layout model, computer product, and method of manufacturing device Jan 28, 2007 Issued
Array ( [id] => 38588 [patent_doc_number] => 07788621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-31 [patent_title] => 'Method and apparatus for creating layout model, computer product, and method of manufacturing device' [patent_app_type] => utility [patent_app_number] => 11/698854 [patent_app_country] => US [patent_app_date] => 2007-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7569 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/788/07788621.pdf [firstpage_image] =>[orig_patent_app_number] => 11698854 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/698854
Method and apparatus for creating layout model, computer product, and method of manufacturing device Jan 28, 2007 Issued
Array ( [id] => 38588 [patent_doc_number] => 07788621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-31 [patent_title] => 'Method and apparatus for creating layout model, computer product, and method of manufacturing device' [patent_app_type] => utility [patent_app_number] => 11/698854 [patent_app_country] => US [patent_app_date] => 2007-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7569 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/788/07788621.pdf [firstpage_image] =>[orig_patent_app_number] => 11698854 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/698854
Method and apparatus for creating layout model, computer product, and method of manufacturing device Jan 28, 2007 Issued
Array ( [id] => 4449105 [patent_doc_number] => 07865857 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-01-04 [patent_title] => 'System and method for improved visualization and debugging of constraint circuit objects' [patent_app_type] => utility [patent_app_number] => 11/657659 [patent_app_country] => US [patent_app_date] => 2007-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 55 [patent_no_of_words] => 21955 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/865/07865857.pdf [firstpage_image] =>[orig_patent_app_number] => 11657659 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/657659
System and method for improved visualization and debugging of constraint circuit objects Jan 22, 2007 Issued
Array ( [id] => 8693326 [patent_doc_number] => 08392862 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-03-05 [patent_title] => 'Structures and methods for optimizing power consumption in an integrated chip design' [patent_app_type] => utility [patent_app_number] => 11/657228 [patent_app_country] => US [patent_app_date] => 2007-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 6909 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 347 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11657228 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/657228
Structures and methods for optimizing power consumption in an integrated chip design Jan 22, 2007 Issued
Array ( [id] => 4990807 [patent_doc_number] => 20070157148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'Circuit layout system for automatically indicating items to wait for modification and method thereof' [patent_app_type] => utility [patent_app_number] => 11/638425 [patent_app_country] => US [patent_app_date] => 2006-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3327 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20070157148.pdf [firstpage_image] =>[orig_patent_app_number] => 11638425 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/638425
Circuit layout system for automatically indicating items to wait for modification and method thereof Dec 13, 2006 Abandoned
Array ( [id] => 5255256 [patent_doc_number] => 20070136712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'Semiconductor design support apparatus' [patent_app_type] => utility [patent_app_number] => 11/635661 [patent_app_country] => US [patent_app_date] => 2006-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 11228 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20070136712.pdf [firstpage_image] =>[orig_patent_app_number] => 11635661 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/635661
Semiconductor design support apparatus Dec 7, 2006 Issued
Array ( [id] => 27583 [patent_doc_number] => 07802214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-21 [patent_title] => 'Methods and apparatuses for timing analysis of electronics circuits' [patent_app_type] => utility [patent_app_number] => 11/635371 [patent_app_country] => US [patent_app_date] => 2006-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4359 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/802/07802214.pdf [firstpage_image] =>[orig_patent_app_number] => 11635371 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/635371
Methods and apparatuses for timing analysis of electronics circuits Dec 6, 2006 Issued
Array ( [id] => 5237937 [patent_doc_number] => 20070130094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-07 [patent_title] => 'Apparatus for rapid model calculation for pattern-dependent variations in a routing system' [patent_app_type] => utility [patent_app_number] => 11/633555 [patent_app_country] => US [patent_app_date] => 2006-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2163 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20070130094.pdf [firstpage_image] =>[orig_patent_app_number] => 11633555 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/633555
Apparatus for rapid model calculation for pattern-dependent variations in a routing system Dec 4, 2006 Abandoned
Array ( [id] => 4837155 [patent_doc_number] => 20080134130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'LOCAL COLORING FOR HIERARCHICAL OPC' [patent_app_type] => utility [patent_app_number] => 11/564957 [patent_app_country] => US [patent_app_date] => 2006-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6634 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20080134130.pdf [firstpage_image] =>[orig_patent_app_number] => 11564957 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/564957
Local coloring for hierarchical OPC Nov 29, 2006 Issued
Array ( [id] => 4837141 [patent_doc_number] => 20080134116 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'METHOD, COMPUTER PROGRAM PRODUCT, AND TOOL FOR TIMING PERFORMANCE OF A HIERARCHICAL CHIP DESIGN HAVING MULTIPLE PARTITION INSTANCES' [patent_app_type] => utility [patent_app_number] => 11/565192 [patent_app_country] => US [patent_app_date] => 2006-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1398 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20080134116.pdf [firstpage_image] =>[orig_patent_app_number] => 11565192 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/565192
METHOD, COMPUTER PROGRAM PRODUCT, AND TOOL FOR TIMING PERFORMANCE OF A HIERARCHICAL CHIP DESIGN HAVING MULTIPLE PARTITION INSTANCES Nov 29, 2006 Abandoned
Array ( [id] => 4837144 [patent_doc_number] => 20080134119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'Automated Electrostatic Discharge Structure Placement and Routing in an Integrated Circuit' [patent_app_type] => utility [patent_app_number] => 11/565023 [patent_app_country] => US [patent_app_date] => 2006-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5514 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20080134119.pdf [firstpage_image] =>[orig_patent_app_number] => 11565023 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/565023
Automated electrostatic discharge structure placement and routing in an integrated circuit Nov 29, 2006 Issued
Array ( [id] => 4837154 [patent_doc_number] => 20080134129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'DESIGN RULE CHECKING FOR ALTERNATING PHASE SHIFT LITHOGRAPHY' [patent_app_type] => utility [patent_app_number] => 11/565195 [patent_app_country] => US [patent_app_date] => 2006-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3736 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20080134129.pdf [firstpage_image] =>[orig_patent_app_number] => 11565195 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/565195
DESIGN RULE CHECKING FOR ALTERNATING PHASE SHIFT LITHOGRAPHY Nov 29, 2006 Abandoned
Array ( [id] => 284234 [patent_doc_number] => 07555737 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-30 [patent_title] => 'Auxiliary method for circuit design' [patent_app_type] => utility [patent_app_number] => 11/564422 [patent_app_country] => US [patent_app_date] => 2006-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 5184 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/555/07555737.pdf [firstpage_image] =>[orig_patent_app_number] => 11564422 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/564422
Auxiliary method for circuit design Nov 28, 2006 Issued
Menu