
Backhean Tiv
Examiner (ID: 5442, Phone: (571)272-5654 , Office: P/2451 )
| Most Active Art Unit | 2459 |
| Art Unit(s) | 2459, 2451, 2151 |
| Total Applications | 1157 |
| Issued Applications | 842 |
| Pending Applications | 79 |
| Abandoned Applications | 250 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 313474
[patent_doc_number] => 07530043
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-05-05
[patent_title] => 'Printed circuit board able to suppress simultaneous switching noise'
[patent_app_type] => utility
[patent_app_number] => 11/563158
[patent_app_country] => US
[patent_app_date] => 2006-11-25
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/530/07530043.pdf
[firstpage_image] =>[orig_patent_app_number] => 11563158
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/563158 | Printed circuit board able to suppress simultaneous switching noise | Nov 24, 2006 | Issued |
Array
(
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[patent_doc_number] => 07600203
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[patent_kind] => B2
[patent_issue_date] => 2009-10-06
[patent_title] => 'Circuit design system and circuit design program'
[patent_app_type] => utility
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[pdf_file] => patents/07/600/07600203.pdf
[firstpage_image] =>[orig_patent_app_number] => 11588372
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/588372 | Circuit design system and circuit design program | Oct 26, 2006 | Issued |
Array
(
[id] => 5231945
[patent_doc_number] => 20070294053
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-12-20
[patent_title] => 'Semiconductor failure analysis apparatus, failure analysis method, and failure analysis program'
[patent_app_type] => utility
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[patent_app_date] => 2006-10-26
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/586719 | Semiconductor failure analysis apparatus, failure analysis method, and failure analysis program | Oct 25, 2006 | Issued |
Array
(
[id] => 4830506
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[patent_issue_date] => 2008-05-29
[patent_title] => 'Method and system for conducting a low-power design exploration'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/588927 | Method and system for conducting a low-power design exploration | Oct 25, 2006 | Issued |
Array
(
[id] => 5122015
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[patent_title] => 'Design method and system for generating behavioral description model'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/586679 | Design method and system for generating behavioral description model | Oct 25, 2006 | Abandoned |
Array
(
[id] => 171997
[patent_doc_number] => 07669165
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-02-23
[patent_title] => 'Method and system for equivalence checking of a low power design'
[patent_app_type] => utility
[patent_app_number] => 11/586879
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[pdf_file] => patents/07/669/07669165.pdf
[firstpage_image] =>[orig_patent_app_number] => 11586879
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/586879 | Method and system for equivalence checking of a low power design | Oct 24, 2006 | Issued |
Array
(
[id] => 4830532
[patent_doc_number] => 20080127020
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[patent_issue_date] => 2008-05-29
[patent_title] => 'System and method for automatic elimination of voltage drop, also known as IR drop, violations of a mask layout block, maintaining the process design rules correctness'
[patent_app_type] => utility
[patent_app_number] => 11/585604
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 11585604
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/585604 | System and method for automatic elimination of voltage drop, also known as IR drop, violations of a mask layout block, maintaining the process design rules correctness | Oct 24, 2006 | Abandoned |
Array
(
[id] => 5034775
[patent_doc_number] => 20070099314
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-03
[patent_title] => 'Modeling device variations in integrated circuit design'
[patent_app_type] => utility
[patent_app_number] => 11/586827
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/586827 | Modeling device variations in integrated circuit design | Oct 23, 2006 | Issued |
Array
(
[id] => 5156090
[patent_doc_number] => 20070038973
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-02-15
[patent_title] => 'Method and apparatus for quickly determining the effect of placing an assist feature at a location in a layout'
[patent_app_type] => utility
[patent_app_number] => 11/584737
[patent_app_country] => US
[patent_app_date] => 2006-10-19
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/584737 | Method and apparatus for quickly determining the effect of placing an assist feature at a location in a layout | Oct 18, 2006 | Issued |
Array
(
[id] => 4882105
[patent_doc_number] => 20080155488
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-06-26
[patent_title] => 'DEVICE FOR AVOIDING TIMING VIOLATIONS RESULTING FROM PROCESS DEFECTS IN A BACKFILLED METAL LAYER OF AN INTEGRATED CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 11/538187
[patent_app_country] => US
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[patent_drawing_sheets_cnt] => 11
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[firstpage_image] =>[orig_patent_app_number] => 11538187
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/538187 | Device for avoiding timing violations resulting from process defects in a backfilled metal layer of an integrated circuit | Oct 2, 2006 | Issued |
Array
(
[id] => 4945625
[patent_doc_number] => 20080082952
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-03
[patent_title] => 'Method of inclusion of sub-resolution assist feature(s)'
[patent_app_type] => utility
[patent_app_number] => 11/540214
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[firstpage_image] =>[orig_patent_app_number] => 11540214
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/540214 | Method of inclusion of sub-resolution assist feature(s) | Sep 28, 2006 | Abandoned |
Array
(
[id] => 4945623
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[patent_issue_date] => 2008-04-03
[patent_title] => 'Differential pair connection arrangement, and method and computer program product for making same'
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Array
(
[id] => 5731979
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[patent_title] => 'Systems and methods for designing and fabricating multi-layer structures having thermal expansion properties'
[patent_app_type] => utility
[patent_app_number] => 11/441600
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/441600 | Systems and methods for designing and fabricating multi-layer structures having thermal expansion properties | Jul 11, 2006 | Abandoned |
Array
(
[id] => 4934936
[patent_doc_number] => 20080005711
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[patent_kind] => A1
[patent_issue_date] => 2008-01-03
[patent_title] => 'METHOD AND APPARATUS FOR APPROXIMATING DIAGONAL LINES IN PLACEMENT'
[patent_app_type] => utility
[patent_app_number] => 11/424840
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/424840 | Method and apparatus for approximating diagonal lines in placement | Jun 15, 2006 | Issued |
Array
(
[id] => 4934942
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[patent_country] => US
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[patent_title] => 'PRIMITIVE CELL METHOD FOR FRONT END PHYSICAL DESIGN'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/423240 | Primitive cell method for front end physical design | Jun 8, 2006 | Issued |
Array
(
[id] => 5891070
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[patent_title] => 'CIRCUIT SYNTHESIS WITH SEQUENTIAL RULES'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/421612 | Circuit synthesis with sequential rules | May 31, 2006 | Issued |
Array
(
[id] => 5232538
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[patent_title] => 'Transferring software assertions to hardware design language code'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/445013 | Transferring software assertions to hardware design language code | May 31, 2006 | Abandoned |
Array
(
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/438644 | Method and apparatus for automatic creation and placement of a floor-plan region | May 21, 2006 | Issued |
Array
(
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