Search

Backhean Tiv

Examiner (ID: 5442, Phone: (571)272-5654 , Office: P/2451 )

Most Active Art Unit
2459
Art Unit(s)
2459, 2451, 2151
Total Applications
1157
Issued Applications
842
Pending Applications
79
Abandoned Applications
250

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 313474 [patent_doc_number] => 07530043 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => 'Printed circuit board able to suppress simultaneous switching noise' [patent_app_type] => utility [patent_app_number] => 11/563158 [patent_app_country] => US [patent_app_date] => 2006-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1750 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/530/07530043.pdf [firstpage_image] =>[orig_patent_app_number] => 11563158 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/563158
Printed circuit board able to suppress simultaneous switching noise Nov 24, 2006 Issued
Array ( [id] => 235174 [patent_doc_number] => 07600203 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-06 [patent_title] => 'Circuit design system and circuit design program' [patent_app_type] => utility [patent_app_number] => 11/588372 [patent_app_country] => US [patent_app_date] => 2006-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 28 [patent_no_of_words] => 15103 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/600/07600203.pdf [firstpage_image] =>[orig_patent_app_number] => 11588372 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/588372
Circuit design system and circuit design program Oct 26, 2006 Issued
Array ( [id] => 5231945 [patent_doc_number] => 20070294053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-20 [patent_title] => 'Semiconductor failure analysis apparatus, failure analysis method, and failure analysis program' [patent_app_type] => utility [patent_app_number] => 11/586719 [patent_app_country] => US [patent_app_date] => 2006-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 14254 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0294/20070294053.pdf [firstpage_image] =>[orig_patent_app_number] => 11586719 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/586719
Semiconductor failure analysis apparatus, failure analysis method, and failure analysis program Oct 25, 2006 Issued
Array ( [id] => 4830506 [patent_doc_number] => 20080126999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'Method and system for conducting a low-power design exploration' [patent_app_type] => utility [patent_app_number] => 11/588927 [patent_app_country] => US [patent_app_date] => 2006-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4049 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20080126999.pdf [firstpage_image] =>[orig_patent_app_number] => 11588927 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/588927
Method and system for conducting a low-power design exploration Oct 25, 2006 Issued
Array ( [id] => 5122015 [patent_doc_number] => 20070143730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'Design method and system for generating behavioral description model' [patent_app_type] => utility [patent_app_number] => 11/586679 [patent_app_country] => US [patent_app_date] => 2006-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3270 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20070143730.pdf [firstpage_image] =>[orig_patent_app_number] => 11586679 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/586679
Design method and system for generating behavioral description model Oct 25, 2006 Abandoned
Array ( [id] => 171997 [patent_doc_number] => 07669165 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-23 [patent_title] => 'Method and system for equivalence checking of a low power design' [patent_app_type] => utility [patent_app_number] => 11/586879 [patent_app_country] => US [patent_app_date] => 2006-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5754 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/669/07669165.pdf [firstpage_image] =>[orig_patent_app_number] => 11586879 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/586879
Method and system for equivalence checking of a low power design Oct 24, 2006 Issued
Array ( [id] => 4830532 [patent_doc_number] => 20080127020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'System and method for automatic elimination of voltage drop, also known as IR drop, violations of a mask layout block, maintaining the process design rules correctness' [patent_app_type] => utility [patent_app_number] => 11/585604 [patent_app_country] => US [patent_app_date] => 2006-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3627 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20080127020.pdf [firstpage_image] =>[orig_patent_app_number] => 11585604 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/585604
System and method for automatic elimination of voltage drop, also known as IR drop, violations of a mask layout block, maintaining the process design rules correctness Oct 24, 2006 Abandoned
Array ( [id] => 5034775 [patent_doc_number] => 20070099314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Modeling device variations in integrated circuit design' [patent_app_type] => utility [patent_app_number] => 11/586827 [patent_app_country] => US [patent_app_date] => 2006-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10724 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20070099314.pdf [firstpage_image] =>[orig_patent_app_number] => 11586827 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/586827
Modeling device variations in integrated circuit design Oct 23, 2006 Issued
Array ( [id] => 5156090 [patent_doc_number] => 20070038973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-15 [patent_title] => 'Method and apparatus for quickly determining the effect of placing an assist feature at a location in a layout' [patent_app_type] => utility [patent_app_number] => 11/584737 [patent_app_country] => US [patent_app_date] => 2006-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6791 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20070038973.pdf [firstpage_image] =>[orig_patent_app_number] => 11584737 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/584737
Method and apparatus for quickly determining the effect of placing an assist feature at a location in a layout Oct 18, 2006 Issued
Array ( [id] => 4882105 [patent_doc_number] => 20080155488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'DEVICE FOR AVOIDING TIMING VIOLATIONS RESULTING FROM PROCESS DEFECTS IN A BACKFILLED METAL LAYER OF AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/538187 [patent_app_country] => US [patent_app_date] => 2006-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4610 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20080155488.pdf [firstpage_image] =>[orig_patent_app_number] => 11538187 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/538187
Device for avoiding timing violations resulting from process defects in a backfilled metal layer of an integrated circuit Oct 2, 2006 Issued
Array ( [id] => 4945625 [patent_doc_number] => 20080082952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-03 [patent_title] => 'Method of inclusion of sub-resolution assist feature(s)' [patent_app_type] => utility [patent_app_number] => 11/540214 [patent_app_country] => US [patent_app_date] => 2006-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 13593 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20080082952.pdf [firstpage_image] =>[orig_patent_app_number] => 11540214 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/540214
Method of inclusion of sub-resolution assist feature(s) Sep 28, 2006 Abandoned
Array ( [id] => 4945623 [patent_doc_number] => 20080082950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-03 [patent_title] => 'Differential pair connection arrangement, and method and computer program product for making same' [patent_app_type] => utility [patent_app_number] => 11/540082 [patent_app_country] => US [patent_app_date] => 2006-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4809 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20080082950.pdf [firstpage_image] =>[orig_patent_app_number] => 11540082 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/540082
Differential pair connection arrangement, and method and computer program product for making same Sep 28, 2006 Issued
Array ( [id] => 5731979 [patent_doc_number] => 20060257096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'Systems and methods for designing and fabricating multi-layer structures having thermal expansion properties' [patent_app_type] => utility [patent_app_number] => 11/441600 [patent_app_country] => US [patent_app_date] => 2006-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 14521 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0257/20060257096.pdf [firstpage_image] =>[orig_patent_app_number] => 11441600 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/441600
Systems and methods for designing and fabricating multi-layer structures having thermal expansion properties Jul 11, 2006 Abandoned
Array ( [id] => 4934936 [patent_doc_number] => 20080005711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'METHOD AND APPARATUS FOR APPROXIMATING DIAGONAL LINES IN PLACEMENT' [patent_app_type] => utility [patent_app_number] => 11/424840 [patent_app_country] => US [patent_app_date] => 2006-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 11260 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20080005711.pdf [firstpage_image] =>[orig_patent_app_number] => 11424840 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/424840
Method and apparatus for approximating diagonal lines in placement Jun 15, 2006 Issued
Array ( [id] => 4934942 [patent_doc_number] => 20080005717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'PRIMITIVE CELL METHOD FOR FRONT END PHYSICAL DESIGN' [patent_app_type] => utility [patent_app_number] => 11/423240 [patent_app_country] => US [patent_app_date] => 2006-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6905 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20080005717.pdf [firstpage_image] =>[orig_patent_app_number] => 11423240 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/423240
Primitive cell method for front end physical design Jun 8, 2006 Issued
Array ( [id] => 5891070 [patent_doc_number] => 20060277021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-07 [patent_title] => 'CIRCUIT SYNTHESIS WITH SEQUENTIAL RULES' [patent_app_type] => utility [patent_app_number] => 11/421612 [patent_app_country] => US [patent_app_date] => 2006-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10347 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20060277021.pdf [firstpage_image] =>[orig_patent_app_number] => 11421612 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/421612
Circuit synthesis with sequential rules May 31, 2006 Issued
Array ( [id] => 5232538 [patent_doc_number] => 20070294647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-20 [patent_title] => 'Transferring software assertions to hardware design language code' [patent_app_type] => utility [patent_app_number] => 11/445013 [patent_app_country] => US [patent_app_date] => 2006-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4341 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0294/20070294647.pdf [firstpage_image] =>[orig_patent_app_number] => 11445013 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/445013
Transferring software assertions to hardware design language code May 31, 2006 Abandoned
Array ( [id] => 5027285 [patent_doc_number] => 20070268731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-22 [patent_title] => 'Layout compiler' [patent_app_type] => utility [patent_app_number] => 11/438777 [patent_app_country] => US [patent_app_date] => 2006-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6511 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20070268731.pdf [firstpage_image] =>[orig_patent_app_number] => 11438777 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/438777
Layout compiler May 21, 2006 Abandoned
Array ( [id] => 5030092 [patent_doc_number] => 20070271539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-22 [patent_title] => 'Method and apparatus for automatic creation and placement of a floor-plan region' [patent_app_type] => utility [patent_app_number] => 11/438644 [patent_app_country] => US [patent_app_date] => 2006-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4844 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20070271539.pdf [firstpage_image] =>[orig_patent_app_number] => 11438644 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/438644
Method and apparatus for automatic creation and placement of a floor-plan region May 21, 2006 Issued
Array ( [id] => 5243905 [patent_doc_number] => 20070022400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'Method, program, and apparatus for designing layout of semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/436520 [patent_app_country] => US [patent_app_date] => 2006-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5137 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20070022400.pdf [firstpage_image] =>[orig_patent_app_number] => 11436520 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/436520
Method, program, and apparatus for designing layout of semiconductor integrated circuit May 18, 2006 Abandoned
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