Search

Backhean Tiv

Examiner (ID: 5442, Phone: (571)272-5654 , Office: P/2451 )

Most Active Art Unit
2459
Art Unit(s)
2459, 2451, 2151
Total Applications
1157
Issued Applications
842
Pending Applications
79
Abandoned Applications
250

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5260809 [patent_doc_number] => 20070214442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'A Method For Predicting Inductance And Self-Resonant Frequency Of A Spiral Inductor' [patent_app_type] => utility [patent_app_number] => 11/435710 [patent_app_country] => US [patent_app_date] => 2006-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3515 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20070214442.pdf [firstpage_image] =>[orig_patent_app_number] => 11435710 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/435710
Method for predicting inductance and self-resonant frequency of a spiral inductor May 17, 2006 Issued
Array ( [id] => 193052 [patent_doc_number] => 07644380 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-01-05 [patent_title] => 'Method for analyzing circuits having MOS devices' [patent_app_type] => utility [patent_app_number] => 11/433960 [patent_app_country] => US [patent_app_date] => 2006-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 9449 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/644/07644380.pdf [firstpage_image] =>[orig_patent_app_number] => 11433960 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/433960
Method for analyzing circuits having MOS devices May 14, 2006 Issued
Array ( [id] => 5706774 [patent_doc_number] => 20060195822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-31 [patent_title] => 'Method and system for debugging an electronic system' [patent_app_type] => utility [patent_app_number] => 11/417355 [patent_app_country] => US [patent_app_date] => 2006-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 29277 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20060195822.pdf [firstpage_image] =>[orig_patent_app_number] => 11417355 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/417355
Method and system for debugging an electronic system May 1, 2006 Issued
Array ( [id] => 5226779 [patent_doc_number] => 20070256046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'Analysis and optimization of manufacturing yield improvements' [patent_app_type] => utility [patent_app_number] => 11/415441 [patent_app_country] => US [patent_app_date] => 2006-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8463 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20070256046.pdf [firstpage_image] =>[orig_patent_app_number] => 11415441 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/415441
Analysis and optimization of manufacturing yield improvements Apr 29, 2006 Abandoned
Array ( [id] => 4577935 [patent_doc_number] => 07823091 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-26 [patent_title] => 'Compilable, reconfigurable network processor' [patent_app_type] => utility [patent_app_number] => 11/413133 [patent_app_country] => US [patent_app_date] => 2006-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6209 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/823/07823091.pdf [firstpage_image] =>[orig_patent_app_number] => 11413133 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/413133
Compilable, reconfigurable network processor Apr 26, 2006 Issued
Array ( [id] => 5226777 [patent_doc_number] => 20070256044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'SYSTEM AND METHOD TO POWER ROUTE HIERARCHICAL DESIGNS THAT EMPLOY MACRO REUSE' [patent_app_type] => utility [patent_app_number] => 11/380236 [patent_app_country] => US [patent_app_date] => 2006-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4138 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20070256044.pdf [firstpage_image] =>[orig_patent_app_number] => 11380236 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/380236
SYSTEM AND METHOD TO POWER ROUTE HIERARCHICAL DESIGNS THAT EMPLOY MACRO REUSE Apr 25, 2006 Abandoned
Array ( [id] => 9999118 [patent_doc_number] => 09043735 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-05-26 [patent_title] => 'Synthesis of fast squarer functional blocks' [patent_app_type] => utility [patent_app_number] => 11/408740 [patent_app_country] => US [patent_app_date] => 2006-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 16721 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11408740 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/408740
Synthesis of fast squarer functional blocks Apr 20, 2006 Issued
Array ( [id] => 223673 [patent_doc_number] => 07610570 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-10-27 [patent_title] => 'Method and mechanism for using systematic local search for SAT solving' [patent_app_type] => utility [patent_app_number] => 11/407864 [patent_app_country] => US [patent_app_date] => 2006-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4449 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/610/07610570.pdf [firstpage_image] =>[orig_patent_app_number] => 11407864 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/407864
Method and mechanism for using systematic local search for SAT solving Apr 18, 2006 Issued
Array ( [id] => 5058847 [patent_doc_number] => 20070061769 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Layout method and layout program for semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 11/401310 [patent_app_country] => US [patent_app_date] => 2006-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5520 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20070061769.pdf [firstpage_image] =>[orig_patent_app_number] => 11401310 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/401310
Layout method and layout program for semiconductor integrated circuit device Apr 10, 2006 Issued
Array ( [id] => 8247240 [patent_doc_number] => 08205186 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-06-19 [patent_title] => 'Incremental modification of instrumentation logic' [patent_app_type] => utility [patent_app_number] => 11/400590 [patent_app_country] => US [patent_app_date] => 2006-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6413 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/205/08205186.pdf [firstpage_image] =>[orig_patent_app_number] => 11400590 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/400590
Incremental modification of instrumentation logic Apr 6, 2006 Issued
Array ( [id] => 860587 [patent_doc_number] => 07376920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-20 [patent_title] => 'Method to monitor critical dimension of IC interconnect' [patent_app_type] => utility [patent_app_number] => 11/398980 [patent_app_country] => US [patent_app_date] => 2006-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5512 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/376/07376920.pdf [firstpage_image] =>[orig_patent_app_number] => 11398980 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/398980
Method to monitor critical dimension of IC interconnect Apr 5, 2006 Issued
Array ( [id] => 832763 [patent_doc_number] => 07401310 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-07-15 [patent_title] => 'Integrated circuit design with cell-based macros' [patent_app_type] => utility [patent_app_number] => 11/397550 [patent_app_country] => US [patent_app_date] => 2006-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 9281 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/401/07401310.pdf [firstpage_image] =>[orig_patent_app_number] => 11397550 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/397550
Integrated circuit design with cell-based macros Apr 3, 2006 Issued
Array ( [id] => 7589208 [patent_doc_number] => 07665056 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-02-16 [patent_title] => 'Method and system for dynamic placement of bond fingers on integrated circuit package' [patent_app_type] => utility [patent_app_number] => 11/354826 [patent_app_country] => US [patent_app_date] => 2006-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6079 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/665/07665056.pdf [firstpage_image] =>[orig_patent_app_number] => 11354826 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/354826
Method and system for dynamic placement of bond fingers on integrated circuit package Feb 15, 2006 Issued
Array ( [id] => 5928351 [patent_doc_number] => 20060242618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-26 [patent_title] => 'Lithographic simulations using graphical processing units' [patent_app_type] => utility [patent_app_number] => 11/354398 [patent_app_country] => US [patent_app_date] => 2006-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3748 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20060242618.pdf [firstpage_image] =>[orig_patent_app_number] => 11354398 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/354398
Lithographic simulations using graphical processing units Feb 13, 2006 Abandoned
Array ( [id] => 5891620 [patent_doc_number] => 20060277234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-07 [patent_title] => 'A compact processor element for a scalable digital logic verification and emulation system' [patent_app_type] => utility [patent_app_number] => 11/307130 [patent_app_country] => US [patent_app_date] => 2006-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2153 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20060277234.pdf [firstpage_image] =>[orig_patent_app_number] => 11307130 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/307130
Compact processor element for a scalable digital logic verification and emulation system Jan 24, 2006 Issued
Array ( [id] => 5217524 [patent_doc_number] => 20070158835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-12 [patent_title] => 'Method for designing interconnect for a new processing technology' [patent_app_type] => utility [patent_app_number] => 11/332566 [patent_app_country] => US [patent_app_date] => 2006-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2475 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20070158835.pdf [firstpage_image] =>[orig_patent_app_number] => 11332566 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/332566
Method for designing interconnect for a new processing technology Jan 11, 2006 Abandoned
Array ( [id] => 5657252 [patent_doc_number] => 20060142988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Design methodology and manufacturing method for semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/318431 [patent_app_country] => US [patent_app_date] => 2005-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10436 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20060142988.pdf [firstpage_image] =>[orig_patent_app_number] => 11318431 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/318431
Design methodology and manufacturing method for semiconductor memory Dec 27, 2005 Abandoned
Array ( [id] => 87959 [patent_doc_number] => 07743356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-22 [patent_title] => 'Method of disposing dummy pattern' [patent_app_type] => utility [patent_app_number] => 11/306392 [patent_app_country] => US [patent_app_date] => 2005-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 9491 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/743/07743356.pdf [firstpage_image] =>[orig_patent_app_number] => 11306392 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/306392
Method of disposing dummy pattern Dec 26, 2005 Issued
Array ( [id] => 5081485 [patent_doc_number] => 20070124709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-31 [patent_title] => 'Method and system for design rule checking for an SiP device' [patent_app_type] => utility [patent_app_number] => 11/287767 [patent_app_country] => US [patent_app_date] => 2005-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7041 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20070124709.pdf [firstpage_image] =>[orig_patent_app_number] => 11287767 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/287767
Method and system for design rule checking for an SiP device Nov 27, 2005 Abandoned
Array ( [id] => 5042348 [patent_doc_number] => 20070094630 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'Power grid design in an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/163520 [patent_app_country] => US [patent_app_date] => 2005-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7682 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20070094630.pdf [firstpage_image] =>[orig_patent_app_number] => 11163520 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/163520
Power grid design in an integrated circuit Oct 20, 2005 Abandoned
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