
Backhean Tiv
Examiner (ID: 5442, Phone: (571)272-5654 , Office: P/2451 )
| Most Active Art Unit | 2459 |
| Art Unit(s) | 2459, 2451, 2151 |
| Total Applications | 1157 |
| Issued Applications | 842 |
| Pending Applications | 79 |
| Abandoned Applications | 250 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 823621
[patent_doc_number] => 07409657
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[patent_kind] => B2
[patent_issue_date] => 2008-08-05
[patent_title] => 'Clock tree layout method for semiconductor integrated circuit'
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[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/243189 | Clock tree layout method for semiconductor integrated circuit | Oct 4, 2005 | Issued |
Array
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[patent_issue_date] => 2006-04-20
[patent_title] => 'Library for computer-based tool and related system and method'
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Array
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[patent_title] => 'Model-based SRAF insertion'
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Array
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[patent_issue_date] => 2009-10-06
[patent_title] => 'Method and apparatus for modular circuit design for a programmable logic device'
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Array
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[patent_title] => 'Shared memory interface in a programmable logic device using partial reconfiguration'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/230879 | Shared memory interface in a programmable logic device using partial reconfiguration | Sep 19, 2005 | Issued |
Array
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[patent_title] => 'Method and system for stencil design for particle beam writing'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/226253 | Method and system for stencil design for particle beam writing | Sep 14, 2005 | Issued |
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[patent_title] => 'Methods, systems, and carrier media for evaluating reticle layout data'
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Array
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[patent_title] => 'Method and system for performing target enlargement in the presence of constraints'
[patent_app_type] => utility
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Array
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[patent_issue_date] => 2006-06-01
[patent_title] => 'Method and device for checking a circuit for adherence to set-up and hold times'
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Array
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[patent_title] => 'Design methodology to support relocatable bit streams for dynamic partial reconfiguration of FPGAs to reduce bit stream memory requirements'
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Array
(
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[patent_title] => 'Method and apparatus for evaluating coverage of circuit, and computer product'
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Array
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Array
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Array
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Array
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Array
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Array
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