Bao Q Truong
Examiner (ID: 6250, Phone: (571)272-2383 , Office: P/2875 )
Most Active Art Unit | 2875 |
Art Unit(s) | 2875, 2187 |
Total Applications | 2222 |
Issued Applications | 1800 |
Pending Applications | 79 |
Abandoned Applications | 342 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 4183519
[patent_doc_number] => 06159833
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-12
[patent_title] => 'Method of forming a contact hole in a semiconductor wafer'
[patent_app_type] => 1
[patent_app_number] => 9/391322
[patent_app_country] => US
[patent_app_date] => 1999-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 1693
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/159/06159833.pdf
[firstpage_image] =>[orig_patent_app_number] => 391322
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/391322 | Method of forming a contact hole in a semiconductor wafer | Sep 7, 1999 | Issued |
Array
(
[id] => 4358874
[patent_doc_number] => 06168999
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-02
[patent_title] => 'Method for fabricating high-performance submicron mosfet with lateral asymmetric channel and a lightly doped drain'
[patent_app_type] => 1
[patent_app_number] => 9/391301
[patent_app_country] => US
[patent_app_date] => 1999-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 2340
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/168/06168999.pdf
[firstpage_image] =>[orig_patent_app_number] => 391301
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/391301 | Method for fabricating high-performance submicron mosfet with lateral asymmetric channel and a lightly doped drain | Sep 6, 1999 | Issued |
Array
(
[id] => 4358934
[patent_doc_number] => 06169003
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-02
[patent_title] => 'Method for forming a MOS device with an elevated source and drain, and having a self-aligned channel input'
[patent_app_type] => 1
[patent_app_number] => 9/375202
[patent_app_country] => US
[patent_app_date] => 1999-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 3015
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 228
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/169/06169003.pdf
[firstpage_image] =>[orig_patent_app_number] => 375202
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/375202 | Method for forming a MOS device with an elevated source and drain, and having a self-aligned channel input | Aug 15, 1999 | Issued |
Array
(
[id] => 4235147
[patent_doc_number] => 06165842
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-26
[patent_title] => 'Method for fabricating a non-volatile memory device using nano-crystal dots'
[patent_app_type] => 1
[patent_app_number] => 9/353321
[patent_app_country] => US
[patent_app_date] => 1999-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 27
[patent_no_of_words] => 1654
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/165/06165842.pdf
[firstpage_image] =>[orig_patent_app_number] => 353321
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/353321 | Method for fabricating a non-volatile memory device using nano-crystal dots | Jul 13, 1999 | Issued |
Array
(
[id] => 4234580
[patent_doc_number] => 06165804
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-26
[patent_title] => 'Scalable high dielectric constant capacitor'
[patent_app_type] => 1
[patent_app_number] => 9/313682
[patent_app_country] => US
[patent_app_date] => 1999-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 13
[patent_no_of_words] => 4141
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/165/06165804.pdf
[firstpage_image] =>[orig_patent_app_number] => 313682
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/313682 | Scalable high dielectric constant capacitor | May 17, 1999 | Issued |
Array
(
[id] => 4155761
[patent_doc_number] => 06156609
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-05
[patent_title] => 'EEPROM device manufacturing method'
[patent_app_type] => 1
[patent_app_number] => 9/298233
[patent_app_country] => US
[patent_app_date] => 1999-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 7
[patent_no_of_words] => 1766
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 190
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/156/06156609.pdf
[firstpage_image] =>[orig_patent_app_number] => 298233
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/298233 | EEPROM device manufacturing method | Apr 22, 1999 | Issued |
Array
(
[id] => 4188145
[patent_doc_number] => 06153467
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-28
[patent_title] => 'Method of fabricating high density buried bit line flash EEPROM memory cell with a shallow trench floating gate'
[patent_app_type] => 1
[patent_app_number] => 9/271736
[patent_app_country] => US
[patent_app_date] => 1999-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 2545
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 214
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/153/06153467.pdf
[firstpage_image] =>[orig_patent_app_number] => 271736
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/271736 | Method of fabricating high density buried bit line flash EEPROM memory cell with a shallow trench floating gate | Mar 17, 1999 | Issued |
Array
(
[id] => 4249291
[patent_doc_number] => 06207472
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-27
[patent_title] => 'Low temperature thin film transistor fabrication'
[patent_app_type] => 1
[patent_app_number] => 9/265161
[patent_app_country] => US
[patent_app_date] => 1999-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 16
[patent_no_of_words] => 4721
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/207/06207472.pdf
[firstpage_image] =>[orig_patent_app_number] => 265161
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/265161 | Low temperature thin film transistor fabrication | Mar 8, 1999 | Issued |
Array
(
[id] => 4145675
[patent_doc_number] => 06063672
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-16
[patent_title] => 'NMOS electrostatic discharge protection device and method for CMOS integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 9/245193
[patent_app_country] => US
[patent_app_date] => 1999-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2483
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/063/06063672.pdf
[firstpage_image] =>[orig_patent_app_number] => 245193
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/245193 | NMOS electrostatic discharge protection device and method for CMOS integrated circuit | Feb 4, 1999 | Issued |
Array
(
[id] => 4286404
[patent_doc_number] => 06211048
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-03
[patent_title] => 'Method of reducing salicide lateral growth'
[patent_app_type] => 1
[patent_app_number] => 9/241792
[patent_app_country] => US
[patent_app_date] => 1999-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 1927
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/211/06211048.pdf
[firstpage_image] =>[orig_patent_app_number] => 241792
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/241792 | Method of reducing salicide lateral growth | Jan 31, 1999 | Issued |
Array
(
[id] => 4357829
[patent_doc_number] => 06191016
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-20
[patent_title] => 'Method of patterning a layer for a gate electrode of a MOS transistor'
[patent_app_type] => 1
[patent_app_number] => 9/226503
[patent_app_country] => US
[patent_app_date] => 1999-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 13
[patent_no_of_words] => 3209
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 225
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/191/06191016.pdf
[firstpage_image] =>[orig_patent_app_number] => 226503
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/226503 | Method of patterning a layer for a gate electrode of a MOS transistor | Jan 4, 1999 | Issued |
Array
(
[id] => 4257956
[patent_doc_number] => 06204102
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-20
[patent_title] => 'Method of fabricating compound semiconductor devices using lift-off of insulating film'
[patent_app_type] => 1
[patent_app_number] => 9/207512
[patent_app_country] => US
[patent_app_date] => 1998-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 13
[patent_no_of_words] => 2321
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/204/06204102.pdf
[firstpage_image] =>[orig_patent_app_number] => 207512
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/207512 | Method of fabricating compound semiconductor devices using lift-off of insulating film | Dec 8, 1998 | Issued |
Array
(
[id] => 4302647
[patent_doc_number] => 06187641
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-13
[patent_title] => 'Lateral MOSFET having a barrier between the source/drain region and the channel region using a heterostructure raised source/drain region'
[patent_app_type] => 1
[patent_app_number] => 9/205151
[patent_app_country] => US
[patent_app_date] => 1998-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 18
[patent_no_of_words] => 4003
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/187/06187641.pdf
[firstpage_image] =>[orig_patent_app_number] => 205151
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/205151 | Lateral MOSFET having a barrier between the source/drain region and the channel region using a heterostructure raised source/drain region | Dec 2, 1998 | Issued |
Array
(
[id] => 4286075
[patent_doc_number] => 06211026
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-03
[patent_title] => 'Methods of forming integrated circuitry, methods of forming elevated source/drain regions of a field effect transistor, and methods of forming field effect transistors'
[patent_app_type] => 1
[patent_app_number] => 9/203541
[patent_app_country] => US
[patent_app_date] => 1998-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 19
[patent_no_of_words] => 4278
[patent_no_of_claims] => 65
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/211/06211026.pdf
[firstpage_image] =>[orig_patent_app_number] => 203541
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/203541 | Methods of forming integrated circuitry, methods of forming elevated source/drain regions of a field effect transistor, and methods of forming field effect transistors | Nov 30, 1998 | Issued |
Array
(
[id] => 4152328
[patent_doc_number] => 06124188
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-26
[patent_title] => 'Semiconductor device and fabrication method using a germanium sacrificial gate electrode plug'
[patent_app_type] => 1
[patent_app_number] => 9/203012
[patent_app_country] => US
[patent_app_date] => 1998-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 10
[patent_no_of_words] => 3400
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/124/06124188.pdf
[firstpage_image] =>[orig_patent_app_number] => 203012
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/203012 | Semiconductor device and fabrication method using a germanium sacrificial gate electrode plug | Nov 30, 1998 | Issued |
Array
(
[id] => 4233039
[patent_doc_number] => 06117743
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-12
[patent_title] => 'Method of manufacturing MOS device using anti reflective coating'
[patent_app_type] => 1
[patent_app_number] => 9/203023
[patent_app_country] => US
[patent_app_date] => 1998-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 13
[patent_no_of_words] => 2444
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/117/06117743.pdf
[firstpage_image] =>[orig_patent_app_number] => 203023
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/203023 | Method of manufacturing MOS device using anti reflective coating | Nov 30, 1998 | Issued |
Array
(
[id] => 4357242
[patent_doc_number] => 06190976
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-20
[patent_title] => 'Fabrication method of semiconductor device using selective epitaxial growth'
[patent_app_type] => 1
[patent_app_number] => 9/198763
[patent_app_country] => US
[patent_app_date] => 1998-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 5976
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 314
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/190/06190976.pdf
[firstpage_image] =>[orig_patent_app_number] => 198763
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/198763 | Fabrication method of semiconductor device using selective epitaxial growth | Nov 23, 1998 | Issued |
Array
(
[id] => 4292045
[patent_doc_number] => 06180464
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-30
[patent_title] => 'Metal oxide semiconductor device with localized laterally doped channel'
[patent_app_type] => 1
[patent_app_number] => 9/198352
[patent_app_country] => US
[patent_app_date] => 1998-11-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 18
[patent_no_of_words] => 2526
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/180/06180464.pdf
[firstpage_image] =>[orig_patent_app_number] => 198352
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/198352 | Metal oxide semiconductor device with localized laterally doped channel | Nov 23, 1998 | Issued |
Array
(
[id] => 4292059
[patent_doc_number] => 06180465
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-30
[patent_title] => 'Method of making high performance MOSFET with channel scaling mask feature'
[patent_app_type] => 1
[patent_app_number] => 9/196853
[patent_app_country] => US
[patent_app_date] => 1998-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 15
[patent_no_of_words] => 5793
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 332
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/180/06180465.pdf
[firstpage_image] =>[orig_patent_app_number] => 196853
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/196853 | Method of making high performance MOSFET with channel scaling mask feature | Nov 19, 1998 | Issued |
Array
(
[id] => 4155000
[patent_doc_number] => 06114194
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-05
[patent_title] => 'Method for fabricating a field device transistor'
[patent_app_type] => 1
[patent_app_number] => 9/192561
[patent_app_country] => US
[patent_app_date] => 1998-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 15
[patent_no_of_words] => 2859
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 13
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/114/06114194.pdf
[firstpage_image] =>[orig_patent_app_number] => 192561
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/192561 | Method for fabricating a field device transistor | Nov 16, 1998 | Issued |