Search

Bao Q Truong

Examiner (ID: 6250, Phone: (571)272-2383 , Office: P/2875 )

Most Active Art Unit
2875
Art Unit(s)
2875, 2187
Total Applications
2222
Issued Applications
1800
Pending Applications
79
Abandoned Applications
342

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4286032 [patent_doc_number] => 06211023 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Method for fabricating a metal-oxide semiconductor transistor' [patent_app_type] => 1 [patent_app_number] => 9/191202 [patent_app_country] => US [patent_app_date] => 1998-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2490 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 344 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/211/06211023.pdf [firstpage_image] =>[orig_patent_app_number] => 191202 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/191202
Method for fabricating a metal-oxide semiconductor transistor Nov 11, 1998 Issued
Array ( [id] => 4237121 [patent_doc_number] => 06090674 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Method of forming a hole in the sub quarter micron range' [patent_app_type] => 1 [patent_app_number] => 9/188523 [patent_app_country] => US [patent_app_date] => 1998-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2193 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/090/06090674.pdf [firstpage_image] =>[orig_patent_app_number] => 188523 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/188523
Method of forming a hole in the sub quarter micron range Nov 8, 1998 Issued
Array ( [id] => 4188450 [patent_doc_number] => 06153485 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Salicide formation on narrow poly lines by pulling back of spacer' [patent_app_type] => 1 [patent_app_number] => 9/188522 [patent_app_country] => US [patent_app_date] => 1998-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3740 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 347 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153485.pdf [firstpage_image] =>[orig_patent_app_number] => 188522 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/188522
Salicide formation on narrow poly lines by pulling back of spacer Nov 8, 1998 Issued
Array ( [id] => 4155159 [patent_doc_number] => 06114206 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Multiple threshold voltage transistor implemented by a damascene process' [patent_app_type] => 1 [patent_app_number] => 9/187171 [patent_app_country] => US [patent_app_date] => 1998-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 4966 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114206.pdf [firstpage_image] =>[orig_patent_app_number] => 187171 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/187171
Multiple threshold voltage transistor implemented by a damascene process Nov 5, 1998 Issued
Array ( [id] => 4292110 [patent_doc_number] => 06180469 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Low resistance salicide technology with reduced silicon consumption' [patent_app_type] => 1 [patent_app_number] => 9/187522 [patent_app_country] => US [patent_app_date] => 1998-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3594 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/180/06180469.pdf [firstpage_image] =>[orig_patent_app_number] => 187522 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/187522
Low resistance salicide technology with reduced silicon consumption Nov 5, 1998 Issued
Array ( [id] => 4417007 [patent_doc_number] => 06194257 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Fabrication method of gate electrode having dual gate insulating film' [patent_app_type] => 1 [patent_app_number] => 9/187003 [patent_app_country] => US [patent_app_date] => 1998-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 2074 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/194/06194257.pdf [firstpage_image] =>[orig_patent_app_number] => 187003 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/187003
Fabrication method of gate electrode having dual gate insulating film Nov 5, 1998 Issued
Array ( [id] => 4094544 [patent_doc_number] => 06096599 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Formation of junctions by diffusion from a doped film into and through a silicide during silicidation' [patent_app_type] => 1 [patent_app_number] => 9/187521 [patent_app_country] => US [patent_app_date] => 1998-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3325 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/096/06096599.pdf [firstpage_image] =>[orig_patent_app_number] => 187521 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/187521
Formation of junctions by diffusion from a doped film into and through a silicide during silicidation Nov 5, 1998 Issued
Array ( [id] => 4083939 [patent_doc_number] => 06162689 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Multi-depth junction formation tailored to silicide formation' [patent_app_type] => 1 [patent_app_number] => 9/187231 [patent_app_country] => US [patent_app_date] => 1998-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3059 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/162/06162689.pdf [firstpage_image] =>[orig_patent_app_number] => 187231 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/187231
Multi-depth junction formation tailored to silicide formation Nov 5, 1998 Issued
Array ( [id] => 4294002 [patent_doc_number] => 06197668 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Ferroelectric-enhanced tantalum pentoxide for dielectric material applications in CMOS devices' [patent_app_type] => 1 [patent_app_number] => 9/187542 [patent_app_country] => US [patent_app_date] => 1998-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2253 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/197/06197668.pdf [firstpage_image] =>[orig_patent_app_number] => 187542 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/187542
Ferroelectric-enhanced tantalum pentoxide for dielectric material applications in CMOS devices Nov 5, 1998 Issued
Array ( [id] => 4246993 [patent_doc_number] => 06221724 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Method of fabricating an integrated circuit having punch-through suppression' [patent_app_type] => 1 [patent_app_number] => 9/187252 [patent_app_country] => US [patent_app_date] => 1998-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3957 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/221/06221724.pdf [firstpage_image] =>[orig_patent_app_number] => 187252 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/187252
Method of fabricating an integrated circuit having punch-through suppression Nov 5, 1998 Issued
Array ( [id] => 4182619 [patent_doc_number] => 06150250 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Conductive layer forming method using etching mask with direction <200>' [patent_app_type] => 1 [patent_app_number] => 9/186811 [patent_app_country] => US [patent_app_date] => 1998-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 6291 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150250.pdf [firstpage_image] =>[orig_patent_app_number] => 186811 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/186811
Conductive layer forming method using etching mask with direction <200> Nov 4, 1998 Issued
Array ( [id] => 4169082 [patent_doc_number] => 06140185 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/185652 [patent_app_country] => US [patent_app_date] => 1998-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 4648 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/140/06140185.pdf [firstpage_image] =>[orig_patent_app_number] => 185652 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/185652
Method of manufacturing semiconductor device Nov 4, 1998 Issued
Array ( [id] => 4101682 [patent_doc_number] => 06100145 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Silicidation with silicon buffer layer and silicon spacers' [patent_app_type] => 1 [patent_app_number] => 9/186073 [patent_app_country] => US [patent_app_date] => 1998-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2909 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100145.pdf [firstpage_image] =>[orig_patent_app_number] => 186073 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/186073
Silicidation with silicon buffer layer and silicon spacers Nov 4, 1998 Issued
Array ( [id] => 4234592 [patent_doc_number] => 06165805 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Scan tool recipe server' [patent_app_type] => 1 [patent_app_number] => 9/182942 [patent_app_country] => US [patent_app_date] => 1998-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2320 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/165/06165805.pdf [firstpage_image] =>[orig_patent_app_number] => 182942 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/182942
Scan tool recipe server Oct 28, 1998 Issued
Array ( [id] => 4293097 [patent_doc_number] => 06197604 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Method for providing cooperative run-to-run control for multi-product and multi-process semiconductor fabrication' [patent_app_type] => 1 [patent_app_number] => 9/164823 [patent_app_country] => US [patent_app_date] => 1998-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7271 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/197/06197604.pdf [firstpage_image] =>[orig_patent_app_number] => 164823 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/164823
Method for providing cooperative run-to-run control for multi-product and multi-process semiconductor fabrication Sep 30, 1998 Issued
Array ( [id] => 4419182 [patent_doc_number] => 06177287 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Simplified inter database communication system' [patent_app_type] => 1 [patent_app_number] => 9/162112 [patent_app_country] => US [patent_app_date] => 1998-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2634 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/177/06177287.pdf [firstpage_image] =>[orig_patent_app_number] => 162112 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/162112
Simplified inter database communication system Sep 27, 1998 Issued
Array ( [id] => 4214511 [patent_doc_number] => 06110788 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Surface channel MOS transistors, methods for making the same, and semiconductor devices containing the same' [patent_app_type] => 1 [patent_app_number] => 9/153931 [patent_app_country] => US [patent_app_date] => 1998-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3578 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/110/06110788.pdf [firstpage_image] =>[orig_patent_app_number] => 153931 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/153931
Surface channel MOS transistors, methods for making the same, and semiconductor devices containing the same Sep 15, 1998 Issued
Array ( [id] => 4232630 [patent_doc_number] => 06117715 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Methods of fabricating integrated circuit field effect transistors by performing multiple implants prior to forming the gate insulating layer thereof' [patent_app_type] => 1 [patent_app_number] => 9/143131 [patent_app_country] => US [patent_app_date] => 1998-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3011 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/117/06117715.pdf [firstpage_image] =>[orig_patent_app_number] => 143131 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/143131
Methods of fabricating integrated circuit field effect transistors by performing multiple implants prior to forming the gate insulating layer thereof Aug 27, 1998 Issued
Array ( [id] => 4235349 [patent_doc_number] => 06165856 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Using an organic layer as an ion implantation mask when forming shallow source/drain region' [patent_app_type] => 1 [patent_app_number] => 9/133291 [patent_app_country] => US [patent_app_date] => 1998-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2505 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/165/06165856.pdf [firstpage_image] =>[orig_patent_app_number] => 133291 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/133291
Using an organic layer as an ion implantation mask when forming shallow source/drain region Aug 11, 1998 Issued
Array ( [id] => 4354696 [patent_doc_number] => 06200868 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Insulated gate type semiconductor device and process for producing the device' [patent_app_type] => 1 [patent_app_number] => 9/126722 [patent_app_country] => US [patent_app_date] => 1998-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 7333 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/200/06200868.pdf [firstpage_image] =>[orig_patent_app_number] => 126722 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/126722
Insulated gate type semiconductor device and process for producing the device Jul 30, 1998 Issued
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