Bao Q Truong
Examiner (ID: 6250, Phone: (571)272-2383 , Office: P/2875 )
Most Active Art Unit | 2875 |
Art Unit(s) | 2875, 2187 |
Total Applications | 2222 |
Issued Applications | 1800 |
Pending Applications | 79 |
Abandoned Applications | 342 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 4358295
[patent_doc_number] => 06168960
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-02
[patent_title] => 'Backside device deprocessing of a flip-chip multi-layer integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 9/126072
[patent_app_country] => US
[patent_app_date] => 1998-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 1548
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/168/06168960.pdf
[firstpage_image] =>[orig_patent_app_number] => 126072
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/126072 | Backside device deprocessing of a flip-chip multi-layer integrated circuit | Jul 29, 1998 | Issued |
Array
(
[id] => 4119049
[patent_doc_number] => 06033231
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-07
[patent_title] => 'Semiconductor device having a pedestal and method of forming'
[patent_app_type] => 1
[patent_app_number] => 9/121812
[patent_app_country] => US
[patent_app_date] => 1998-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 8250
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/033/06033231.pdf
[firstpage_image] =>[orig_patent_app_number] => 121812
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/121812 | Semiconductor device having a pedestal and method of forming | Jul 23, 1998 | Issued |
Array
(
[id] => 4145793
[patent_doc_number] => 06063681
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-16
[patent_title] => 'Silicide formation using two metalizations'
[patent_app_type] => 1
[patent_app_number] => 9/118823
[patent_app_country] => US
[patent_app_date] => 1998-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 26
[patent_no_of_words] => 3107
[patent_no_of_claims] => 15
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[patent_words_short_claim] => 176
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/063/06063681.pdf
[firstpage_image] =>[orig_patent_app_number] => 118823
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/118823 | Silicide formation using two metalizations | Jul 19, 1998 | Issued |
Array
(
[id] => 4081042
[patent_doc_number] => 06054370
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-25
[patent_title] => 'Method of delaminating a pre-fabricated transistor layer from a substrate for placement on another wafer'
[patent_app_type] => 1
[patent_app_number] => 9/107393
[patent_app_country] => US
[patent_app_date] => 1998-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 2447
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 83
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/054/06054370.pdf
[firstpage_image] =>[orig_patent_app_number] => 107393
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/107393 | Method of delaminating a pre-fabricated transistor layer from a substrate for placement on another wafer | Jun 29, 1998 | Issued |
Array
(
[id] => 4131252
[patent_doc_number] => 06121098
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-19
[patent_title] => 'Semiconductor manufacturing method'
[patent_app_type] => 1
[patent_app_number] => 9/107672
[patent_app_country] => US
[patent_app_date] => 1998-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 2166
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/121/06121098.pdf
[firstpage_image] =>[orig_patent_app_number] => 107672
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/107672 | Semiconductor manufacturing method | Jun 29, 1998 | Issued |
Array
(
[id] => 4080741
[patent_doc_number] => 06054349
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-25
[patent_title] => 'Single-electron device including therein nanocrystals'
[patent_app_type] => 1
[patent_app_number] => 9/095883
[patent_app_country] => US
[patent_app_date] => 1998-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
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[patent_no_of_words] => 6629
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[pdf_file] => patents/06/054/06054349.pdf
[firstpage_image] =>[orig_patent_app_number] => 095883
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/095883 | Single-electron device including therein nanocrystals | Jun 10, 1998 | Issued |
Array
(
[id] => 4136409
[patent_doc_number] => 06015727
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-18
[patent_title] => 'Damascene formation of borderless contact MOS transistors'
[patent_app_type] => 1
[patent_app_number] => 9/093221
[patent_app_country] => US
[patent_app_date] => 1998-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 19
[patent_no_of_words] => 1455
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 16
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/015/06015727.pdf
[firstpage_image] =>[orig_patent_app_number] => 093221
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/093221 | Damascene formation of borderless contact MOS transistors | Jun 7, 1998 | Issued |
Array
(
[id] => 4097787
[patent_doc_number] => 06048765
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-11
[patent_title] => 'Method of forming high density buried bit line flash EEPROM memory cell with a shallow trench floating gate'
[patent_app_type] => 1
[patent_app_number] => 9/089897
[patent_app_country] => US
[patent_app_date] => 1998-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 2527
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 168
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/048/06048765.pdf
[firstpage_image] =>[orig_patent_app_number] => 089897
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/089897 | Method of forming high density buried bit line flash EEPROM memory cell with a shallow trench floating gate | Jun 2, 1998 | Issued |
Array
(
[id] => 4087314
[patent_doc_number] => 06133122
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-17
[patent_title] => 'Method of fabricating semiconductor device for preventing rising-up of siliside'
[patent_app_type] => 1
[patent_app_number] => 9/089666
[patent_app_country] => US
[patent_app_date] => 1998-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 3721
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/133/06133122.pdf
[firstpage_image] =>[orig_patent_app_number] => 089666
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/089666 | Method of fabricating semiconductor device for preventing rising-up of siliside | Jun 2, 1998 | Issued |
Array
(
[id] => 4172529
[patent_doc_number] => 06083798
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-04
[patent_title] => 'Method of producing a metal oxide semiconductor device with raised source/drain'
[patent_app_type] => 1
[patent_app_number] => 9/084322
[patent_app_country] => US
[patent_app_date] => 1998-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 2323
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[pdf_file] => patents/06/083/06083798.pdf
[firstpage_image] =>[orig_patent_app_number] => 084322
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/084322 | Method of producing a metal oxide semiconductor device with raised source/drain | May 25, 1998 | Issued |
Array
(
[id] => 4188682
[patent_doc_number] => 06153501
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-28
[patent_title] => 'Method of reducing overetch during the formation of a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/082083
[patent_app_country] => US
[patent_app_date] => 1998-05-20
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/153/06153501.pdf
[firstpage_image] =>[orig_patent_app_number] => 082083
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/082083 | Method of reducing overetch during the formation of a semiconductor device | May 19, 1998 | Issued |
Array
(
[id] => 4182937
[patent_doc_number] => 06159794
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-12
[patent_title] => 'Methods for removing silicide residue in a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/076662
[patent_app_country] => US
[patent_app_date] => 1998-05-12
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/159/06159794.pdf
[firstpage_image] =>[orig_patent_app_number] => 076662
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/076662 | Methods for removing silicide residue in a semiconductor device | May 11, 1998 | Issued |
Array
(
[id] => 4291451
[patent_doc_number] => 06180422
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-30
[patent_title] => 'Endpoint detection by chemical reaction'
[patent_app_type] => 1
[patent_app_number] => 9/073602
[patent_app_country] => US
[patent_app_date] => 1998-05-06
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/180/06180422.pdf
[firstpage_image] =>[orig_patent_app_number] => 073602
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/073602 | Endpoint detection by chemical reaction | May 5, 1998 | Issued |
Array
(
[id] => 4097891
[patent_doc_number] => 06048772
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-11
[patent_title] => 'Method for fabricating a lateral RF MOS device with an non-diffusion source-backside connection'
[patent_app_type] => 1
[patent_app_number] => 9/072393
[patent_app_country] => US
[patent_app_date] => 1998-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/048/06048772.pdf
[firstpage_image] =>[orig_patent_app_number] => 072393
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/072393 | Method for fabricating a lateral RF MOS device with an non-diffusion source-backside connection | May 3, 1998 | Issued |
Array
(
[id] => 4214470
[patent_doc_number] => 06110785
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-29
[patent_title] => 'Formulation of high performance transistors using gate trim etch process'
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[patent_app_number] => 9/069533
[patent_app_country] => US
[patent_app_date] => 1998-04-29
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/110/06110785.pdf
[firstpage_image] =>[orig_patent_app_number] => 069533
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/069533 | Formulation of high performance transistors using gate trim etch process | Apr 28, 1998 | Issued |
Array
(
[id] => 4172779
[patent_doc_number] => 06083815
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-04
[patent_title] => 'Method of gate etching with thin gate oxide'
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[patent_app_number] => 9/067263
[patent_app_country] => US
[patent_app_date] => 1998-04-27
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/083/06083815.pdf
[firstpage_image] =>[orig_patent_app_number] => 067263
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/067263 | Method of gate etching with thin gate oxide | Apr 26, 1998 | Issued |
Array
(
[id] => 4099861
[patent_doc_number] => 06066530
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-23
[patent_title] => 'Oxygen implant self-aligned, floating gate and isolation structure'
[patent_app_type] => 1
[patent_app_number] => 9/057992
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[patent_app_date] => 1998-04-09
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[pdf_file] => patents/06/066/06066530.pdf
[firstpage_image] =>[orig_patent_app_number] => 057992
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/057992 | Oxygen implant self-aligned, floating gate and isolation structure | Apr 8, 1998 | Issued |
Array
(
[id] => 4063719
[patent_doc_number] => 06008079
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-28
[patent_title] => 'Method for forming a high density shallow trench contactless nonvolatile memory'
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[pdf_file] => patents/06/008/06008079.pdf
[firstpage_image] =>[orig_patent_app_number] => 048549
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/048549 | Method for forming a high density shallow trench contactless nonvolatile memory | Mar 24, 1998 | Issued |
Array
(
[id] => 3910808
[patent_doc_number] => 06001697
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-14
[patent_title] => 'Process for manufacturing semiconductor devices having raised doped regions'
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[pdf_file] => patents/06/001/06001697.pdf
[firstpage_image] =>[orig_patent_app_number] => 046594
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/046594 | Process for manufacturing semiconductor devices having raised doped regions | Mar 23, 1998 | Issued |
Array
(
[id] => 4155202
[patent_doc_number] => 06114209
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/114/06114209.pdf
[firstpage_image] =>[orig_patent_app_number] => 045102
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/045102 | Method of fabricating semiconductor devices with raised doped region structures | Mar 18, 1998 | Issued |