Search

Bao Q Truong

Examiner (ID: 6250, Phone: (571)272-2383 , Office: P/2875 )

Most Active Art Unit
2875
Art Unit(s)
2875, 2187
Total Applications
2222
Issued Applications
1800
Pending Applications
79
Abandoned Applications
342

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3944033 [patent_doc_number] => 05976966 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Converting a hydrogen silsesquioxane film to an oxide using a first heat treatment and a second heat treatment with the second heat treatment using rapid thermal processing' [patent_app_type] => 1 [patent_app_number] => 8/964580 [patent_app_country] => US [patent_app_date] => 1997-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2576 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/976/05976966.pdf [firstpage_image] =>[orig_patent_app_number] => 964580 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/964580
Converting a hydrogen silsesquioxane film to an oxide using a first heat treatment and a second heat treatment with the second heat treatment using rapid thermal processing Nov 4, 1997 Issued
Array ( [id] => 4069656 [patent_doc_number] => 05933723 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Capacitor constructions and semiconductor processing method of forming capacitor constructions' [patent_app_type] => 1 [patent_app_number] => 8/962483 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1833 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933723.pdf [firstpage_image] =>[orig_patent_app_number] => 962483 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/962483
Capacitor constructions and semiconductor processing method of forming capacitor constructions Oct 30, 1997 Issued
Array ( [id] => 4181015 [patent_doc_number] => 06020223 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Method of manufacturing a thin film transistor with reduced parasitic capacitance and reduced feed-through voltage' [patent_app_type] => 1 [patent_app_number] => 8/959590 [patent_app_country] => US [patent_app_date] => 1997-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 34 [patent_no_of_words] => 8242 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/020/06020223.pdf [firstpage_image] =>[orig_patent_app_number] => 959590 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/959590
Method of manufacturing a thin film transistor with reduced parasitic capacitance and reduced feed-through voltage Oct 28, 1997 Issued
Array ( [id] => 4174621 [patent_doc_number] => 06019796 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Method of manufacturing a thin film transistor with reduced parasitic capacitance and reduced feed-through voltage' [patent_app_type] => 1 [patent_app_number] => 8/960025 [patent_app_country] => US [patent_app_date] => 1997-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 34 [patent_no_of_words] => 8248 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/019/06019796.pdf [firstpage_image] =>[orig_patent_app_number] => 960025 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/960025
Method of manufacturing a thin film transistor with reduced parasitic capacitance and reduced feed-through voltage Oct 28, 1997 Issued
Array ( [id] => 4084353 [patent_doc_number] => 06025214 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Fusible link structure for semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 8/956192 [patent_app_country] => US [patent_app_date] => 1997-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 4 [patent_no_of_words] => 3349 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/025/06025214.pdf [firstpage_image] =>[orig_patent_app_number] => 956192 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/956192
Fusible link structure for semiconductor devices Oct 21, 1997 Issued
Array ( [id] => 3976244 [patent_doc_number] => 05937295 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Nano-structure memory device' [patent_app_type] => 1 [patent_app_number] => 8/947283 [patent_app_country] => US [patent_app_date] => 1997-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4823 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/937/05937295.pdf [firstpage_image] =>[orig_patent_app_number] => 947283 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/947283
Nano-structure memory device Oct 6, 1997 Issued
Array ( [id] => 3910528 [patent_doc_number] => 06001678 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Insulated gate semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/937163 [patent_app_country] => US [patent_app_date] => 1997-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 31 [patent_no_of_words] => 12183 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 523 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/001/06001678.pdf [firstpage_image] =>[orig_patent_app_number] => 937163 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/937163
Insulated gate semiconductor device Sep 24, 1997 Issued
Array ( [id] => 3937043 [patent_doc_number] => 05981319 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Method of forming a T-shaped gate' [patent_app_type] => 1 [patent_app_number] => 8/935121 [patent_app_country] => US [patent_app_date] => 1997-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2717 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/981/05981319.pdf [firstpage_image] =>[orig_patent_app_number] => 935121 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/935121
Method of forming a T-shaped gate Sep 21, 1997 Issued
Array ( [id] => 4190860 [patent_doc_number] => 06043114 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 8/934774 [patent_app_country] => US [patent_app_date] => 1997-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 32 [patent_no_of_words] => 15422 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/043/06043114.pdf [firstpage_image] =>[orig_patent_app_number] => 934774 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/934774
Process for manufacturing a semiconductor wafer, a semiconductor wafer, process for manufacturing a semiconductor integrated circuit device, and semiconductor integrated circuit device Sep 21, 1997 Issued
Array ( [id] => 4222033 [patent_doc_number] => 06010930 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Vertically oriented structure with sloped opening and method for etching' [patent_app_type] => 1 [patent_app_number] => 8/928041 [patent_app_country] => US [patent_app_date] => 1997-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4095 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/010/06010930.pdf [firstpage_image] =>[orig_patent_app_number] => 928041 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/928041
Vertically oriented structure with sloped opening and method for etching Sep 10, 1997 Issued
Array ( [id] => 4069906 [patent_doc_number] => 05933739 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Self-aligned silicidation structure and method of formation thereof' [patent_app_type] => 1 [patent_app_number] => 8/927479 [patent_app_country] => US [patent_app_date] => 1997-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 3116 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933739.pdf [firstpage_image] =>[orig_patent_app_number] => 927479 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/927479
Self-aligned silicidation structure and method of formation thereof Sep 10, 1997 Issued
Array ( [id] => 3944919 [patent_doc_number] => 05953580 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Method of manufacturing a vacuum device' [patent_app_type] => 1 [patent_app_number] => 8/925197 [patent_app_country] => US [patent_app_date] => 1997-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2491 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/953/05953580.pdf [firstpage_image] =>[orig_patent_app_number] => 925197 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/925197
Method of manufacturing a vacuum device Sep 7, 1997 Issued
Array ( [id] => 4131624 [patent_doc_number] => 06121123 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Gate pattern formation using a BARC as a hardmask' [patent_app_type] => 1 [patent_app_number] => 8/924573 [patent_app_country] => US [patent_app_date] => 1997-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 2071 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121123.pdf [firstpage_image] =>[orig_patent_app_number] => 924573 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/924573
Gate pattern formation using a BARC as a hardmask Sep 4, 1997 Issued
Array ( [id] => 4181329 [patent_doc_number] => 06020242 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Effective silicide blocking' [patent_app_type] => 1 [patent_app_number] => 8/926590 [patent_app_country] => US [patent_app_date] => 1997-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 4950 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/020/06020242.pdf [firstpage_image] =>[orig_patent_app_number] => 926590 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/926590
Effective silicide blocking Sep 3, 1997 Issued
Array ( [id] => 4116767 [patent_doc_number] => 06071784 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Annealing of silicon oxynitride and silicon nitride films to eliminate high temperature charge loss' [patent_app_type] => 1 [patent_app_number] => 8/921003 [patent_app_country] => US [patent_app_date] => 1997-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5606 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/071/06071784.pdf [firstpage_image] =>[orig_patent_app_number] => 921003 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/921003
Annealing of silicon oxynitride and silicon nitride films to eliminate high temperature charge loss Aug 28, 1997 Issued
Array ( [id] => 3941341 [patent_doc_number] => 05989944 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Method of fabricating self-aligned thin film transistor using laser irradiation' [patent_app_type] => 1 [patent_app_number] => 8/920005 [patent_app_country] => US [patent_app_date] => 1997-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 3082 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/989/05989944.pdf [firstpage_image] =>[orig_patent_app_number] => 920005 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/920005
Method of fabricating self-aligned thin film transistor using laser irradiation Aug 28, 1997 Issued
Array ( [id] => 4156045 [patent_doc_number] => 06156630 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Titanium boride gate electrode and interconnect and methods regarding same' [patent_app_type] => 1 [patent_app_number] => 8/916275 [patent_app_country] => US [patent_app_date] => 1997-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5816 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/156/06156630.pdf [firstpage_image] =>[orig_patent_app_number] => 916275 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/916275
Titanium boride gate electrode and interconnect and methods regarding same Aug 21, 1997 Issued
Array ( [id] => 4031363 [patent_doc_number] => 05907777 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Method for forming field effect transistors having different threshold voltages and devices formed thereby' [patent_app_type] => 1 [patent_app_number] => 8/903671 [patent_app_country] => US [patent_app_date] => 1997-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3300 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907777.pdf [firstpage_image] =>[orig_patent_app_number] => 903671 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/903671
Method for forming field effect transistors having different threshold voltages and devices formed thereby Jul 30, 1997 Issued
Array ( [id] => 4233152 [patent_doc_number] => 06117751 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Method for manufacturing a mis structure on silicon carbide (SiC)' [patent_app_type] => 1 [patent_app_number] => 8/896439 [patent_app_country] => US [patent_app_date] => 1997-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2666 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/117/06117751.pdf [firstpage_image] =>[orig_patent_app_number] => 896439 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/896439
Method for manufacturing a mis structure on silicon carbide (SiC) Jul 17, 1997 Issued
Array ( [id] => 3935125 [patent_doc_number] => 05972765 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Use of deuterated materials in semiconductor processing' [patent_app_type] => 1 [patent_app_number] => 8/895049 [patent_app_country] => US [patent_app_date] => 1997-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5207 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/972/05972765.pdf [firstpage_image] =>[orig_patent_app_number] => 895049 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/895049
Use of deuterated materials in semiconductor processing Jul 15, 1997 Issued
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