Bao Q Truong

Array ( [id] => 4116728 [patent_doc_number] => 06071781 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Method of fabricating lateral MOS transistor' [patent_app_type] => 1 [patent_app_number] => 8/892223 [patent_app_country] => US [patent_app_date] => 1997-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 4130 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/071/06071781.pdf [firstpage_image] =>[orig_patent_app_number] => 892223 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4187969 [patent_doc_number] => 06153454 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Convex device with selectively doped channel' [patent_app_type] => 1 [patent_app_number] => 8/890063 [patent_app_country] => US [patent_app_date] => 1997-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 4770 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153454.pdf [firstpage_image] =>[orig_patent_app_number] => 890063 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4101749 [patent_doc_number] => 06100149 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Method for rapid thermal processing (RTP) of silicon substrates' [patent_app_type] => 1 [patent_app_number] => 8/886215 [patent_app_country] => US [patent_app_date] => 1997-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3383 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100149.pdf [firstpage_image] =>[orig_patent_app_number] => 886215 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4050431 [patent_doc_number] => 05943571 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Method for manufacturing fine structures' [patent_app_type] => 1 [patent_app_number] => 8/883571 [patent_app_country] => US [patent_app_date] => 1997-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2536 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943571.pdf [firstpage_image] =>[orig_patent_app_number] => 883571 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4057202 [patent_doc_number] => 05895245 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Plasma ash for silicon surface preparation' [patent_app_type] => 1 [patent_app_number] => 8/877095 [patent_app_country] => US [patent_app_date] => 1997-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2780 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/895/05895245.pdf [firstpage_image] =>[orig_patent_app_number] => 877095 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4107359 [patent_doc_number] => 06057191 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Process for the fabrication of integrated circuits with contacts self-aligned to active areas' [patent_app_type] => 1 [patent_app_number] => 8/877335 [patent_app_country] => US [patent_app_date] => 1997-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 6 [patent_no_of_words] => 1893 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057191.pdf [firstpage_image] =>[orig_patent_app_number] => 877335 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4098085 [patent_doc_number] => 06048785 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Semiconductor fabrication method of combining a plurality of fields defined by a reticle image using segment stitching' [patent_app_type] => 1 [patent_app_number] => 8/876628 [patent_app_country] => US [patent_app_date] => 1997-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 5071 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/048/06048785.pdf [firstpage_image] =>[orig_patent_app_number] => 876628 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4145729 [patent_doc_number] => 06063676 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Mosfet with raised source and drain regions' [patent_app_type] => 1 [patent_app_number] => 8/871139 [patent_app_country] => US [patent_app_date] => 1997-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5632 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/063/06063676.pdf [firstpage_image] =>[orig_patent_app_number] => 871139 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4080616 [patent_doc_number] => 06054340 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Method for forming a cavity capable of accessing deep fuse structures and device containing the same' [patent_app_type] => 1 [patent_app_number] => 8/870286 [patent_app_country] => US [patent_app_date] => 1997-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3578 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/054/06054340.pdf [firstpage_image] =>[orig_patent_app_number] => 870286 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3934815 [patent_doc_number] => 05972745 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Method or forming self-aligned halo-isolated wells' [patent_app_type] => 1 [patent_app_number] => 8/866674 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1676 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/972/05972745.pdf [firstpage_image] =>[orig_patent_app_number] => 866674 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3937754 [patent_doc_number] => 05981369 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Semiconductor integrated circuit device and process for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 8/865864 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 58 [patent_no_of_words] => 10869 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/981/05981369.pdf [firstpage_image] =>[orig_patent_app_number] => 865864 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4037820 [patent_doc_number] => 05908312 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Semiconductor device fabrication' [patent_app_type] => 1 [patent_app_number] => 8/864220 [patent_app_country] => US [patent_app_date] => 1997-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3064 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/908/05908312.pdf [firstpage_image] =>[orig_patent_app_number] => 864220 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4070159 [patent_doc_number] => 05970326 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Thin film transistor films made with anodized film and reverse-anodized etching technique' [patent_app_type] => 1 [patent_app_number] => 8/861346 [patent_app_country] => US [patent_app_date] => 1997-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 4488 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/970/05970326.pdf [firstpage_image] =>[orig_patent_app_number] => 861346 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4356866 [patent_doc_number] => 06190949 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Silicon thin film, group of silicon single crystal grains and formation process thereof, and semiconductor device, flash memory cell and fabrication process thereof' [patent_app_type] => 1 [patent_app_number] => 8/861197 [patent_app_country] => US [patent_app_date] => 1997-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 8754 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/190/06190949.pdf [firstpage_image] =>[orig_patent_app_number] => 861197 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4183175 [patent_doc_number] => 06159811 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Methods for patterning microelectronic structures using chlorine, oxygen, and fluorine' [patent_app_type] => 1 [patent_app_number] => 8/857754 [patent_app_country] => US [patent_app_date] => 1997-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 4489 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/159/06159811.pdf [firstpage_image] =>[orig_patent_app_number] => 857754 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3944288 [patent_doc_number] => 05998270 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Formation of oxynitride and polysilicon layers in a single reaction chamber' [patent_app_type] => 1 [patent_app_number] => 8/856545 [patent_app_country] => US [patent_app_date] => 1997-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3056 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/998/05998270.pdf [firstpage_image] =>[orig_patent_app_number] => 856545 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4038872 [patent_doc_number] => 05926707 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Methods for forming integrated circuit memory devices having deep storage electrode contact regions therein for improving refresh characteristics' [patent_app_type] => 1 [patent_app_number] => 8/846075 [patent_app_country] => US [patent_app_date] => 1997-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 24 [patent_no_of_words] => 4627 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926707.pdf [firstpage_image] =>[orig_patent_app_number] => 846075 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4172250 [patent_doc_number] => 06083780 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Semiconductor device and method of fabrication thereof' [patent_app_type] => 1 [patent_app_number] => 8/847668 [patent_app_country] => US [patent_app_date] => 1997-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 20 [patent_no_of_words] => 5024 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/083/06083780.pdf [firstpage_image] =>[orig_patent_app_number] => 847668 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3910821 [patent_doc_number] => 06001698 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'MOS transistor and fabrication process for the same' [patent_app_type] => 1 [patent_app_number] => 8/842655 [patent_app_country] => US [patent_app_date] => 1997-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 24 [patent_no_of_words] => 6855 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/001/06001698.pdf [firstpage_image] =>[orig_patent_app_number] => 842655 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4012276 [patent_doc_number] => 05879994 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Self-aligned method of fabricating terrace gate DMOS transistor' [patent_app_type] => 1 [patent_app_number] => 8/842661 [patent_app_country] => US [patent_app_date] => 1997-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 3539 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/879/05879994.pdf [firstpage_image] =>[orig_patent_app_number] => 842661 [rel_patent_id] =>[rel_patent_doc_number] =>)