Search

Bao Q Truong

Examiner (ID: 6250, Phone: (571)272-2383 , Office: P/2875 )

Most Active Art Unit
2875
Art Unit(s)
2875, 2187
Total Applications
2222
Issued Applications
1800
Pending Applications
79
Abandoned Applications
342

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4107824 [patent_doc_number] => 06057221 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Laser-induced cutting of metal interconnect' [patent_app_type] => 1 [patent_app_number] => 8/825808 [patent_app_country] => US [patent_app_date] => 1997-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 5546 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057221.pdf [firstpage_image] =>[orig_patent_app_number] => 825808 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/825808
Laser-induced cutting of metal interconnect Apr 2, 1997 Issued
Array ( [id] => 3999824 [patent_doc_number] => 05950109 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Methods of depositing films on semiconductor wafers using partial deposition and reloading techniques' [patent_app_type] => 1 [patent_app_number] => 8/825118 [patent_app_country] => US [patent_app_date] => 1997-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3691 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/950/05950109.pdf [firstpage_image] =>[orig_patent_app_number] => 825118 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/825118
Methods of depositing films on semiconductor wafers using partial deposition and reloading techniques Mar 26, 1997 Issued
Array ( [id] => 4117470 [patent_doc_number] => 06071832 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Method for manufacturing a reliable semiconductor device using ECR-CVD and implanting hydrogen ions into an active region' [patent_app_type] => 1 [patent_app_number] => 8/822117 [patent_app_country] => US [patent_app_date] => 1997-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 2935 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/071/06071832.pdf [firstpage_image] =>[orig_patent_app_number] => 822117 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/822117
Method for manufacturing a reliable semiconductor device using ECR-CVD and implanting hydrogen ions into an active region Mar 20, 1997 Issued
Array ( [id] => 3944789 [patent_doc_number] => 05998303 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Semiconductor device making method' [patent_app_type] => 1 [patent_app_number] => 8/819727 [patent_app_country] => US [patent_app_date] => 1997-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3791 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/998/05998303.pdf [firstpage_image] =>[orig_patent_app_number] => 819727 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/819727
Semiconductor device making method Mar 17, 1997 Issued
Array ( [id] => 4064198 [patent_doc_number] => 06008111 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/816887 [patent_app_country] => US [patent_app_date] => 1997-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 58 [patent_no_of_words] => 5983 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/008/06008111.pdf [firstpage_image] =>[orig_patent_app_number] => 816887 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/816887
Method of manufacturing semiconductor device Mar 12, 1997 Issued
Array ( [id] => 4181071 [patent_doc_number] => 06020227 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Fabrication of multiple field-effect transistor structure having local threshold-adjust doping' [patent_app_type] => 1 [patent_app_number] => 8/812509 [patent_app_country] => US [patent_app_date] => 1997-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 49 [patent_no_of_words] => 17959 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/020/06020227.pdf [firstpage_image] =>[orig_patent_app_number] => 812509 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/812509
Fabrication of multiple field-effect transistor structure having local threshold-adjust doping Mar 6, 1997 Issued
Array ( [id] => 3945398 [patent_doc_number] => 05953613 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'High performance MOSFET with a source removed from the semiconductor substrate and fabrication method thereof' [patent_app_type] => 1 [patent_app_number] => 8/811415 [patent_app_country] => US [patent_app_date] => 1997-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 6574 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/953/05953613.pdf [firstpage_image] =>[orig_patent_app_number] => 811415 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/811415
High performance MOSFET with a source removed from the semiconductor substrate and fabrication method thereof Mar 3, 1997 Issued
Array ( [id] => 3945250 [patent_doc_number] => 05953605 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Fabrication process of semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/808543 [patent_app_country] => US [patent_app_date] => 1997-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5797 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/953/05953605.pdf [firstpage_image] =>[orig_patent_app_number] => 808543 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/808543
Fabrication process of semiconductor device Feb 27, 1997 Issued
Array ( [id] => 4050559 [patent_doc_number] => 05943579 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Method for forming a diffusion region in a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/799233 [patent_app_country] => US [patent_app_date] => 1997-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 2737 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943579.pdf [firstpage_image] =>[orig_patent_app_number] => 799233 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/799233
Method for forming a diffusion region in a semiconductor device Feb 13, 1997 Issued
Array ( [id] => 3950858 [patent_doc_number] => 05899747 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Method for forming a tapered spacer' [patent_app_type] => 1 [patent_app_number] => 8/789121 [patent_app_country] => US [patent_app_date] => 1997-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 1642 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/899/05899747.pdf [firstpage_image] =>[orig_patent_app_number] => 789121 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/789121
Method for forming a tapered spacer Jan 26, 1997 Issued
Array ( [id] => 3954893 [patent_doc_number] => 05935875 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Dual insulating layer methods for forming integrated circuit gates and conductive contacts' [patent_app_type] => 1 [patent_app_number] => 8/785091 [patent_app_country] => US [patent_app_date] => 1997-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3984 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/935/05935875.pdf [firstpage_image] =>[orig_patent_app_number] => 785091 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/785091
Dual insulating layer methods for forming integrated circuit gates and conductive contacts Jan 20, 1997 Issued
Array ( [id] => 4063930 [patent_doc_number] => 06008092 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Short channel IGBT with improved forward voltage drop and improved switching power loss' [patent_app_type] => 1 [patent_app_number] => 8/786023 [patent_app_country] => US [patent_app_date] => 1997-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3584 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 343 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/008/06008092.pdf [firstpage_image] =>[orig_patent_app_number] => 786023 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/786023
Short channel IGBT with improved forward voltage drop and improved switching power loss Jan 20, 1997 Issued
Array ( [id] => 4152707 [patent_doc_number] => 06107117 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Method of making an organic thin film transistor' [patent_app_type] => 1 [patent_app_number] => 8/770535 [patent_app_country] => US [patent_app_date] => 1996-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3365 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/107/06107117.pdf [firstpage_image] =>[orig_patent_app_number] => 770535 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/770535
Method of making an organic thin film transistor Dec 19, 1996 Issued
Array ( [id] => 3966996 [patent_doc_number] => 05956588 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'High withstand voltage transistor and method for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 8/763093 [patent_app_country] => US [patent_app_date] => 1996-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4151 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956588.pdf [firstpage_image] =>[orig_patent_app_number] => 763093 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/763093
High withstand voltage transistor and method for manufacturing the same Dec 9, 1996 Issued
Menu