Search

Bao Q Vu

Examiner (ID: 16323)

Most Active Art Unit
2838
Art Unit(s)
2111, 2838
Total Applications
1819
Issued Applications
1578
Pending Applications
63
Abandoned Applications
178

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 675974 [patent_doc_number] => 07093090 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-15 [patent_title] => 'Method for creating a virtual data copy of a volume being restored' [patent_app_type] => utility [patent_app_number] => 11/264072 [patent_app_country] => US [patent_app_date] => 2005-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5094 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/093/07093090.pdf [firstpage_image] =>[orig_patent_app_number] => 11264072 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/264072
Method for creating a virtual data copy of a volume being restored Oct 31, 2005 Issued
Array ( [id] => 626372 [patent_doc_number] => 07139888 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-21 [patent_title] => 'Data processing system' [patent_app_type] => utility [patent_app_number] => 10/971147 [patent_app_country] => US [patent_app_date] => 2004-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 23 [patent_no_of_words] => 8926 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/139/07139888.pdf [firstpage_image] =>[orig_patent_app_number] => 10971147 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/971147
Data processing system Oct 24, 2004 Issued
Array ( [id] => 7222610 [patent_doc_number] => 20050055515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Method and apparatus for performing distributed processing of program code' [patent_app_type] => utility [patent_app_number] => 10/969557 [patent_app_country] => US [patent_app_date] => 2004-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6918 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20050055515.pdf [firstpage_image] =>[orig_patent_app_number] => 10969557 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/969557
Method and apparatus for performing distributed processing of program code Oct 18, 2004 Issued
Array ( [id] => 7160230 [patent_doc_number] => 20050027951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Method for supporting multi-level striping of non-homogeneous memory to maximize concurrency' [patent_app_type] => utility [patent_app_number] => 10/928046 [patent_app_country] => US [patent_app_date] => 2004-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 14225 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20050027951.pdf [firstpage_image] =>[orig_patent_app_number] => 10928046 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/928046
Method for supporting multi-level striping of non-homogeneous memory to maximize concurrency Aug 26, 2004 Issued
Array ( [id] => 615721 [patent_doc_number] => 07149852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-12 [patent_title] => 'System and method for blocking data responses' [patent_app_type] => utility [patent_app_number] => 10/761034 [patent_app_country] => US [patent_app_date] => 2004-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 10143 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/149/07149852.pdf [firstpage_image] =>[orig_patent_app_number] => 10761034 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/761034
System and method for blocking data responses Jan 19, 2004 Issued
Array ( [id] => 623243 [patent_doc_number] => 07143245 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-28 [patent_title] => 'System and method for read migratory optimization in a cache coherency protocol' [patent_app_type] => utility [patent_app_number] => 10/761044 [patent_app_country] => US [patent_app_date] => 2004-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 9076 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/143/07143245.pdf [firstpage_image] =>[orig_patent_app_number] => 10761044 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/761044
System and method for read migratory optimization in a cache coherency protocol Jan 19, 2004 Issued
Array ( [id] => 975427 [patent_doc_number] => 06938128 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-30 [patent_title] => 'System and method for reducing memory latency during read requests' [patent_app_type] => utility [patent_app_number] => 10/725897 [patent_app_country] => US [patent_app_date] => 2003-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 11177 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/938/06938128.pdf [firstpage_image] =>[orig_patent_app_number] => 10725897 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/725897
System and method for reducing memory latency during read requests Dec 1, 2003 Issued
Array ( [id] => 695288 [patent_doc_number] => 07076632 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-11 [patent_title] => 'Fast paging of a large memory block' [patent_app_type] => utility [patent_app_number] => 10/687252 [patent_app_country] => US [patent_app_date] => 2003-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4735 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/076/07076632.pdf [firstpage_image] =>[orig_patent_app_number] => 10687252 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/687252
Fast paging of a large memory block Oct 15, 2003 Issued
Array ( [id] => 7271336 [patent_doc_number] => 20040059854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-25 [patent_title] => 'Dynamic priority external transaction system' [patent_app_type] => new [patent_app_number] => 10/667457 [patent_app_country] => US [patent_app_date] => 2003-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3640 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20040059854.pdf [firstpage_image] =>[orig_patent_app_number] => 10667457 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/667457
Dynamic priority external transaction system Sep 22, 2003 Issued
Array ( [id] => 7605713 [patent_doc_number] => 07100009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-29 [patent_title] => 'Method and system for selective memory coalescing across memory heap boundaries' [patent_app_type] => utility [patent_app_number] => 10/666794 [patent_app_country] => US [patent_app_date] => 2003-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2653 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/100/07100009.pdf [firstpage_image] =>[orig_patent_app_number] => 10666794 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/666794
Method and system for selective memory coalescing across memory heap boundaries Sep 17, 2003 Issued
Array ( [id] => 7013449 [patent_doc_number] => 20050066113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-24 [patent_title] => 'Method and memory controller for adaptive row management within a memory subsystem' [patent_app_type] => utility [patent_app_number] => 10/666814 [patent_app_country] => US [patent_app_date] => 2003-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3542 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20050066113.pdf [firstpage_image] =>[orig_patent_app_number] => 10666814 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/666814
Method and memory controller for adaptive row management within a memory subsystem Sep 17, 2003 Issued
Array ( [id] => 7282282 [patent_doc_number] => 20040064659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Storage apparatus system and method of data backup' [patent_app_type] => new [patent_app_number] => 10/657010 [patent_app_country] => US [patent_app_date] => 2003-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 15641 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20040064659.pdf [firstpage_image] =>[orig_patent_app_number] => 10657010 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/657010
Storage apparatus system and method of data backup Sep 4, 2003 Issued
Array ( [id] => 933318 [patent_doc_number] => 06981095 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-27 [patent_title] => 'Hot replace power control sequence logic' [patent_app_type] => utility [patent_app_number] => 10/634576 [patent_app_country] => US [patent_app_date] => 2003-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 13787 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/981/06981095.pdf [firstpage_image] =>[orig_patent_app_number] => 10634576 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/634576
Hot replace power control sequence logic Aug 4, 2003 Issued
Array ( [id] => 787611 [patent_doc_number] => 06990556 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-24 [patent_title] => 'System and method for simultaneous access of the same doubleword in cache storage' [patent_app_type] => utility [patent_app_number] => 10/436221 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2428 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/990/06990556.pdf [firstpage_image] =>[orig_patent_app_number] => 10436221 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/436221
System and method for simultaneous access of the same doubleword in cache storage May 11, 2003 Issued
Array ( [id] => 7436119 [patent_doc_number] => 20040230745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'Parallel cache interleave accesses with address-sliced directories' [patent_app_type] => new [patent_app_number] => 10/436217 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3282 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20040230745.pdf [firstpage_image] =>[orig_patent_app_number] => 10436217 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/436217
Parallel cache interleave accesses with address-sliced directories May 11, 2003 Issued
Array ( [id] => 684670 [patent_doc_number] => 07085897 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'Memory management for a symmetric multiprocessor computer system' [patent_app_type] => utility [patent_app_number] => 10/436491 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5695 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/085/07085897.pdf [firstpage_image] =>[orig_patent_app_number] => 10436491 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/436491
Memory management for a symmetric multiprocessor computer system May 11, 2003 Issued
Array ( [id] => 6731928 [patent_doc_number] => 20030188118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-02 [patent_title] => 'System and method to improve speed and reduce memory allocation for set top box boot-up' [patent_app_type] => new [patent_app_number] => 10/390832 [patent_app_country] => US [patent_app_date] => 2003-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3026 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20030188118.pdf [firstpage_image] =>[orig_patent_app_number] => 10390832 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/390832
System and method to improve speed and reduce memory allocation for set top box boot-up Mar 16, 2003 Issued
Array ( [id] => 782197 [patent_doc_number] => 06996664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-07 [patent_title] => 'Ternary content addressable memory with enhanced priority matching' [patent_app_type] => utility [patent_app_number] => 10/349796 [patent_app_country] => US [patent_app_date] => 2003-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5924 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/996/06996664.pdf [firstpage_image] =>[orig_patent_app_number] => 10349796 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/349796
Ternary content addressable memory with enhanced priority matching Jan 21, 2003 Issued
Array ( [id] => 739662 [patent_doc_number] => 07039789 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-02 [patent_title] => 'Circular addressing algorithms providing increased compatibility with one or more higher-level programming languages' [patent_app_type] => utility [patent_app_number] => 10/349225 [patent_app_country] => US [patent_app_date] => 2003-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2297 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/039/07039789.pdf [firstpage_image] =>[orig_patent_app_number] => 10349225 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/349225
Circular addressing algorithms providing increased compatibility with one or more higher-level programming languages Jan 21, 2003 Issued
Array ( [id] => 705130 [patent_doc_number] => 07069407 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-06-27 [patent_title] => 'Method and apparatus for a multi-channel high speed framer' [patent_app_type] => utility [patent_app_number] => 10/327456 [patent_app_country] => US [patent_app_date] => 2002-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4048 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/069/07069407.pdf [firstpage_image] =>[orig_patent_app_number] => 10327456 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/327456
Method and apparatus for a multi-channel high speed framer Dec 19, 2002 Issued
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