Barbara J Bullock

Array ( [id] => 7597280 [patent_doc_number] => 07619297 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-17 [patent_title] => 'Electronic device including an inductor' [patent_app_type] => utility [patent_app_number] => 12/390133 [patent_app_country] => US [patent_app_date] => 2009-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 9689 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/619/07619297.pdf [firstpage_image] =>[orig_patent_app_number] => 12390133 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5385824 [patent_doc_number] => 20090227069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-10 [patent_title] => 'Method and device for fabricating an assembly of at least two microelectronic chips' [patent_app_type] => utility [patent_app_number] => 12/379357 [patent_app_country] => US [patent_app_date] => 2009-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3465 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20090227069.pdf [firstpage_image] =>[orig_patent_app_number] => 12379357 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8283407 [patent_doc_number] => 08217509 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-10 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/372198 [patent_app_country] => US [patent_app_date] => 2009-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 4 [patent_no_of_words] => 18899 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12372198 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5578650 [patent_doc_number] => 20090173996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-09 [patent_title] => 'Recess Gate Type Transistor' [patent_app_type] => utility [patent_app_number] => 12/371788 [patent_app_country] => US [patent_app_date] => 2009-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3999 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20090173996.pdf [firstpage_image] =>[orig_patent_app_number] => 12371788 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7729365 [patent_doc_number] => 08101463 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-24 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/370437 [patent_app_country] => US [patent_app_date] => 2009-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3308 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/101/08101463.pdf [firstpage_image] =>[orig_patent_app_number] => 12370437 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5572927 [patent_doc_number] => 20090140288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-04 [patent_title] => 'HIGH ION/IOFF SOI MOSFET USING BODY VOLTAGE CONTROL' [patent_app_type] => utility [patent_app_number] => 12/368171 [patent_app_country] => US [patent_app_date] => 2009-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4373 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20090140288.pdf [firstpage_image] =>[orig_patent_app_number] => 12368171 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5303630 [patent_doc_number] => 20090298282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-03 [patent_title] => 'Methods of Forming Interlayer Dielectrics Having Air Gaps' [patent_app_type] => utility [patent_app_number] => 12/364598 [patent_app_country] => US [patent_app_date] => 2009-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3009 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0298/20090298282.pdf [firstpage_image] =>[orig_patent_app_number] => 12364598 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3993 [patent_doc_number] => 07816157 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-19 [patent_title] => 'Method of producing semiconductor optical device' [patent_app_type] => utility [patent_app_number] => 12/364718 [patent_app_country] => US [patent_app_date] => 2009-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 8648 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/816/07816157.pdf [firstpage_image] =>[orig_patent_app_number] => 12364718 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5572893 [patent_doc_number] => 20090140254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-04 [patent_title] => 'THIN FILM TRANSISTOR AND FLAT PANEL DISPLAY DEVICE INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/365090 [patent_app_country] => US [patent_app_date] => 2009-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5817 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20090140254.pdf [firstpage_image] =>[orig_patent_app_number] => 12365090 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6324399 [patent_doc_number] => 20100197135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE WITH METAL-CONTAINING CAP LAYERS' [patent_app_type] => utility [patent_app_number] => 12/363868 [patent_app_country] => US [patent_app_date] => 2009-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6434 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20100197135.pdf [firstpage_image] =>[orig_patent_app_number] => 12363868 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5379885 [patent_doc_number] => 20090191724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-30 [patent_title] => 'Substrate Heating Apparatus, Heating Method, and Semiconductor Device Manufacturing Method' [patent_app_type] => utility [patent_app_number] => 12/360378 [patent_app_country] => US [patent_app_date] => 2009-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4875 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20090191724.pdf [firstpage_image] =>[orig_patent_app_number] => 12360378 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5514972 [patent_doc_number] => 20090215279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'ORGANIC/INORGANIC HYBRID THIN FILM PASSIVATION LAYER FOR BLOCKING MOISTURE/OXYGEN TRANSMISSION AND IMPROVING GAS BARRIER PROPERTY' [patent_app_type] => utility [patent_app_number] => 12/360567 [patent_app_country] => US [patent_app_date] => 2009-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5765 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20090215279.pdf [firstpage_image] =>[orig_patent_app_number] => 12360567 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6633971 [patent_doc_number] => 20100173502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-08 [patent_title] => 'LOW k1 HOLE PRINTING USING TWO INTERSECTING FEATURES' [patent_app_type] => utility [patent_app_number] => 12/349617 [patent_app_country] => US [patent_app_date] => 2009-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4730 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20100173502.pdf [firstpage_image] =>[orig_patent_app_number] => 12349617 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7741896 [patent_doc_number] => 08106458 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-31 [patent_title] => 'SOI CMOS circuits with substrate bias' [patent_app_type] => utility [patent_app_number] => 12/348391 [patent_app_country] => US [patent_app_date] => 2009-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4102 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/106/08106458.pdf [firstpage_image] =>[orig_patent_app_number] => 12348391 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 152336 [patent_doc_number] => 07683443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-23 [patent_title] => 'MOS devices with multi-layer gate stack' [patent_app_type] => utility [patent_app_number] => 12/347061 [patent_app_country] => US [patent_app_date] => 2008-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 29 [patent_no_of_words] => 6311 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/683/07683443.pdf [firstpage_image] =>[orig_patent_app_number] => 12347061 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8446222 [patent_doc_number] => 08288274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-16 [patent_title] => 'Method of forming noble metal layer using ozone reaction gas' [patent_app_type] => utility [patent_app_number] => 12/318468 [patent_app_country] => US [patent_app_date] => 2008-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 11399 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12318468 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 33128 [patent_doc_number] => 07785916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-31 [patent_title] => 'Image sensor and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/344507 [patent_app_country] => US [patent_app_date] => 2008-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3642 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/785/07785916.pdf [firstpage_image] =>[orig_patent_app_number] => 12344507 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7503314 [patent_doc_number] => 08034689 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-11 [patent_title] => 'Method for fabricating a semiconductor device and the semiconductor device made thereof' [patent_app_type] => utility [patent_app_number] => 12/340298 [patent_app_country] => US [patent_app_date] => 2008-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 25 [patent_no_of_words] => 10379 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/034/08034689.pdf [firstpage_image] =>[orig_patent_app_number] => 12340298 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8214889 [patent_doc_number] => 08193567 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-05 [patent_title] => 'Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby' [patent_app_type] => utility [patent_app_number] => 12/333248 [patent_app_country] => US [patent_app_date] => 2008-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 5354 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/193/08193567.pdf [firstpage_image] =>[orig_patent_app_number] => 12333248 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5395111 [patent_doc_number] => 20090315174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-24 [patent_title] => 'Semiconductor Die Separation Method' [patent_app_type] => utility [patent_app_number] => 12/323288 [patent_app_country] => US [patent_app_date] => 2008-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10903 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20090315174.pdf [firstpage_image] =>[orig_patent_app_number] => 12323288 [rel_patent_id] =>[rel_patent_doc_number] =>)