Search

Barbara J Bullock

Examiner (ID: 9881)

Most Active Art Unit
2901
Art Unit(s)
2900, 2912, 2901, 2902
Total Applications
4468
Issued Applications
4372
Pending Applications
0
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5389097 [patent_doc_number] => 20090206409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/219880 [patent_app_country] => US [patent_app_date] => 2008-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6891 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20090206409.pdf [firstpage_image] =>[orig_patent_app_number] => 12219880 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/219880
Semiconductor device Jul 29, 2008 Issued
Array ( [id] => 63674 [patent_doc_number] => 07759189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-20 [patent_title] => 'Method of manufacturing a dual contact trench capacitor' [patent_app_type] => utility [patent_app_number] => 12/181338 [patent_app_country] => US [patent_app_date] => 2008-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 2886 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/759/07759189.pdf [firstpage_image] =>[orig_patent_app_number] => 12181338 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/181338
Method of manufacturing a dual contact trench capacitor Jul 28, 2008 Issued
Array ( [id] => 4506687 [patent_doc_number] => 07915077 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-29 [patent_title] => 'Methods of making metal core foldover package structures' [patent_app_type] => utility [patent_app_number] => 12/180880 [patent_app_country] => US [patent_app_date] => 2008-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8140 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/915/07915077.pdf [firstpage_image] =>[orig_patent_app_number] => 12180880 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/180880
Methods of making metal core foldover package structures Jul 27, 2008 Issued
Array ( [id] => 6352632 [patent_doc_number] => 20100022063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-28 [patent_title] => 'METHOD OF FORMING ON-CHIP PASSIVE ELEMENT' [patent_app_type] => utility [patent_app_number] => 12/180789 [patent_app_country] => US [patent_app_date] => 2008-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4025 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20100022063.pdf [firstpage_image] =>[orig_patent_app_number] => 12180789 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/180789
METHOD OF FORMING ON-CHIP PASSIVE ELEMENT Jul 27, 2008 Abandoned
Array ( [id] => 4499553 [patent_doc_number] => 07948072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-24 [patent_title] => 'Wafer-to-wafer stacking' [patent_app_type] => utility [patent_app_number] => 12/180360 [patent_app_country] => US [patent_app_date] => 2008-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3145 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/948/07948072.pdf [firstpage_image] =>[orig_patent_app_number] => 12180360 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/180360
Wafer-to-wafer stacking Jul 24, 2008 Issued
Array ( [id] => 5391787 [patent_doc_number] => 20090209100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'FABRICATION METHOD FOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/179379 [patent_app_country] => US [patent_app_date] => 2008-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2511 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20090209100.pdf [firstpage_image] =>[orig_patent_app_number] => 12179379 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/179379
Fabrication method for memory device Jul 23, 2008 Issued
Array ( [id] => 5290545 [patent_doc_number] => 20090023275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-22 [patent_title] => 'METHOD FOR FORMING SILICON WELLS OF DIFFERENT CRYSTALLOGRAPHIC ORIENTATIONS' [patent_app_type] => utility [patent_app_number] => 12/175877 [patent_app_country] => US [patent_app_date] => 2008-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1933 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20090023275.pdf [firstpage_image] =>[orig_patent_app_number] => 12175877 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/175877
Method for forming silicon wells of different crystallographic orientations Jul 17, 2008 Issued
Array ( [id] => 5290511 [patent_doc_number] => 20090023241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-22 [patent_title] => 'CLEAN RATE IMPROVEMENT BY PRESSURE CONTROLLED REMOTE PLASMA SOURCE' [patent_app_type] => utility [patent_app_number] => 12/174408 [patent_app_country] => US [patent_app_date] => 2008-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4537 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20090023241.pdf [firstpage_image] =>[orig_patent_app_number] => 12174408 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/174408
CLEAN RATE IMPROVEMENT BY PRESSURE CONTROLLED REMOTE PLASMA SOURCE Jul 15, 2008 Abandoned
Array ( [id] => 5416481 [patent_doc_number] => 20090042368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-12 [patent_title] => 'Wafer processing method' [patent_app_type] => utility [patent_app_number] => 12/219137 [patent_app_country] => US [patent_app_date] => 2008-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6078 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20090042368.pdf [firstpage_image] =>[orig_patent_app_number] => 12219137 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/219137
Wafer processing method Jul 15, 2008 Issued
Array ( [id] => 7712051 [patent_doc_number] => 08093112 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-10 [patent_title] => 'Method for manufacturing display device' [patent_app_type] => utility [patent_app_number] => 12/219018 [patent_app_country] => US [patent_app_date] => 2008-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 98 [patent_no_of_words] => 33374 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/093/08093112.pdf [firstpage_image] =>[orig_patent_app_number] => 12219018 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/219018
Method for manufacturing display device Jul 14, 2008 Issued
Array ( [id] => 7724257 [patent_doc_number] => 08097527 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-17 [patent_title] => 'Method of forming epitaxial layer' [patent_app_type] => utility [patent_app_number] => 12/171157 [patent_app_country] => US [patent_app_date] => 2008-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3954 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/097/08097527.pdf [firstpage_image] =>[orig_patent_app_number] => 12171157 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/171157
Method of forming epitaxial layer Jul 9, 2008 Issued
Array ( [id] => 4856483 [patent_doc_number] => 20080265333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'STRUCTURE AND METHOD FOR ENHANCED TRIPLE WELL LATCHUP ROBUSTNESS' [patent_app_type] => utility [patent_app_number] => 12/169667 [patent_app_country] => US [patent_app_date] => 2008-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8182 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20080265333.pdf [firstpage_image] =>[orig_patent_app_number] => 12169667 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/169667
STRUCTURE AND METHOD FOR ENHANCED TRIPLE WELL LATCHUP ROBUSTNESS Jul 8, 2008 Abandoned
Array ( [id] => 5310296 [patent_doc_number] => 20090017577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'Methods of Forming Phase Change Memory Devices Having Bottom Electrodes' [patent_app_type] => utility [patent_app_number] => 12/170038 [patent_app_country] => US [patent_app_date] => 2008-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 20424 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20090017577.pdf [firstpage_image] =>[orig_patent_app_number] => 12170038 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/170038
Methods of forming phase change memory devices having bottom electrodes Jul 8, 2008 Issued
Array ( [id] => 1076895 [patent_doc_number] => 07615407 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-11-10 [patent_title] => 'Methods and systems for packaging integrated circuits with integrated passive components' [patent_app_type] => utility [patent_app_number] => 12/166938 [patent_app_country] => US [patent_app_date] => 2008-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 27 [patent_no_of_words] => 5310 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/615/07615407.pdf [firstpage_image] =>[orig_patent_app_number] => 12166938 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/166938
Methods and systems for packaging integrated circuits with integrated passive components Jul 1, 2008 Issued
Array ( [id] => 8875675 [patent_doc_number] => 08470640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-25 [patent_title] => 'Method of fabricating stacked semiconductor package with localized cavities for wire bonding' [patent_app_type] => utility [patent_app_number] => 12/165297 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 24 [patent_no_of_words] => 5045 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12165297 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/165297
Method of fabricating stacked semiconductor package with localized cavities for wire bonding Jun 29, 2008 Issued
Array ( [id] => 5461732 [patent_doc_number] => 20090321932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'Coreless substrate package with symmetric external dielectric layers' [patent_app_type] => utility [patent_app_number] => 12/217068 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4439 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0321/20090321932.pdf [firstpage_image] =>[orig_patent_app_number] => 12217068 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/217068
Coreless substrate package with symmetric external dielectric layers Jun 29, 2008 Abandoned
Array ( [id] => 4960143 [patent_doc_number] => 20080274568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-06 [patent_title] => 'Reticle and method of fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/213908 [patent_app_country] => US [patent_app_date] => 2008-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2345 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0274/20080274568.pdf [firstpage_image] =>[orig_patent_app_number] => 12213908 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/213908
Method of fabricating semiconductor device Jun 25, 2008 Issued
Array ( [id] => 4859756 [patent_doc_number] => 20080268606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'Semiconductor device manufacturing method and semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/213624 [patent_app_country] => US [patent_app_date] => 2008-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4431 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20080268606.pdf [firstpage_image] =>[orig_patent_app_number] => 12213624 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/213624
Semiconductor device manufacturing method and semiconductor device Jun 22, 2008 Issued
Array ( [id] => 62773 [patent_doc_number] => 07763507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-27 [patent_title] => 'Stressed interlayer dielectric with reduced probability for void generation in a semiconductor device by using an intermediate etch control layer of increased thickness' [patent_app_type] => utility [patent_app_number] => 12/135478 [patent_app_country] => US [patent_app_date] => 2008-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 8151 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/763/07763507.pdf [firstpage_image] =>[orig_patent_app_number] => 12135478 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/135478
Stressed interlayer dielectric with reduced probability for void generation in a semiconductor device by using an intermediate etch control layer of increased thickness Jun 8, 2008 Issued
Array ( [id] => 5349524 [patent_doc_number] => 20090004885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/155638 [patent_app_country] => US [patent_app_date] => 2008-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5980 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20090004885.pdf [firstpage_image] =>[orig_patent_app_number] => 12155638 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/155638
Method for fabricating semiconductor device Jun 5, 2008 Abandoned
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