Search

Barbara J Bullock

Examiner (ID: 9881)

Most Active Art Unit
2901
Art Unit(s)
2900, 2912, 2901, 2902
Total Applications
4468
Issued Applications
4372
Pending Applications
0
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 411580 [patent_doc_number] => 07282437 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-16 [patent_title] => 'Insulating tube, semiconductor device employing the tube, and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/244293 [patent_app_country] => US [patent_app_date] => 2005-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 25 [patent_no_of_words] => 8646 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/282/07282437.pdf [firstpage_image] =>[orig_patent_app_number] => 11244293 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/244293
Insulating tube, semiconductor device employing the tube, and method of manufacturing the same Oct 5, 2005 Issued
Array ( [id] => 5145665 [patent_doc_number] => 20070045719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-01 [patent_title] => 'Multi-purpose semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/244463 [patent_app_country] => US [patent_app_date] => 2005-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5554 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20070045719.pdf [firstpage_image] =>[orig_patent_app_number] => 11244463 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/244463
Multi-purpose semiconductor device Oct 5, 2005 Abandoned
Array ( [id] => 289320 [patent_doc_number] => 07547936 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-16 [patent_title] => 'Semiconductor memory devices including offset active regions' [patent_app_type] => utility [patent_app_number] => 11/246594 [patent_app_country] => US [patent_app_date] => 2005-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 27 [patent_no_of_words] => 8005 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/547/07547936.pdf [firstpage_image] =>[orig_patent_app_number] => 11246594 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/246594
Semiconductor memory devices including offset active regions Oct 5, 2005 Issued
Array ( [id] => 499619 [patent_doc_number] => 07208800 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-24 [patent_title] => 'Silicon-on-insulator substrate, fabricating method thereof, and method for fabricating floating structure using the same' [patent_app_type] => utility [patent_app_number] => 11/242824 [patent_app_country] => US [patent_app_date] => 2005-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 2699 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/208/07208800.pdf [firstpage_image] =>[orig_patent_app_number] => 11242824 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/242824
Silicon-on-insulator substrate, fabricating method thereof, and method for fabricating floating structure using the same Oct 4, 2005 Issued
Array ( [id] => 5838244 [patent_doc_number] => 20060118902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Lateral semiconductor device and method for producing the same' [patent_app_type] => utility [patent_app_number] => 11/242084 [patent_app_country] => US [patent_app_date] => 2005-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6532 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20060118902.pdf [firstpage_image] =>[orig_patent_app_number] => 11242084 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/242084
Lateral semiconductor device and method for producing the same Oct 3, 2005 Issued
Array ( [id] => 518030 [patent_doc_number] => 07189625 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-13 [patent_title] => 'Micromachine and manufacturing method' [patent_app_type] => utility [patent_app_number] => 11/243550 [patent_app_country] => US [patent_app_date] => 2005-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 28 [patent_no_of_words] => 5210 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/189/07189625.pdf [firstpage_image] =>[orig_patent_app_number] => 11243550 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/243550
Micromachine and manufacturing method Oct 3, 2005 Issued
Array ( [id] => 5796447 [patent_doc_number] => 20060033124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-16 [patent_title] => 'Method for fabrication of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/240380 [patent_app_country] => US [patent_app_date] => 2005-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 8292 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20060033124.pdf [firstpage_image] =>[orig_patent_app_number] => 11240380 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/240380
Method for fabrication of semiconductor device Oct 2, 2005 Abandoned
Array ( [id] => 861297 [patent_doc_number] => 07372101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-13 [patent_title] => 'Sub-lithographics opening for back contact or back gate' [patent_app_type] => utility [patent_app_number] => 11/239834 [patent_app_country] => US [patent_app_date] => 2005-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 11 [patent_no_of_words] => 2420 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/372/07372101.pdf [firstpage_image] =>[orig_patent_app_number] => 11239834 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/239834
Sub-lithographics opening for back contact or back gate Sep 29, 2005 Issued
Array ( [id] => 408786 [patent_doc_number] => 07285830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-23 [patent_title] => 'Lateral bipolar junction transistor in CMOS flow' [patent_app_type] => utility [patent_app_number] => 11/239794 [patent_app_country] => US [patent_app_date] => 2005-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 4389 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/285/07285830.pdf [firstpage_image] =>[orig_patent_app_number] => 11239794 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/239794
Lateral bipolar junction transistor in CMOS flow Sep 29, 2005 Issued
Array ( [id] => 303895 [patent_doc_number] => 07535035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-19 [patent_title] => 'Cross-point nonvolatile memory devices using binary metal oxide layer as data storage material layer and methods of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/241604 [patent_app_country] => US [patent_app_date] => 2005-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4600 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/535/07535035.pdf [firstpage_image] =>[orig_patent_app_number] => 11241604 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/241604
Cross-point nonvolatile memory devices using binary metal oxide layer as data storage material layer and methods of fabricating the same Sep 29, 2005 Issued
Array ( [id] => 5133719 [patent_doc_number] => 20070075348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-05 [patent_title] => 'High density, high Q capacitor on top of a protective layer' [patent_app_type] => utility [patent_app_number] => 11/239244 [patent_app_country] => US [patent_app_date] => 2005-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5668 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20070075348.pdf [firstpage_image] =>[orig_patent_app_number] => 11239244 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/239244
High density, high Q capacitor on top of a protective layer Sep 29, 2005 Abandoned
Array ( [id] => 315160 [patent_doc_number] => 07525130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-28 [patent_title] => 'Polarization-doped field effect transistors (POLFETS) and materials and methods for making the same' [patent_app_type] => utility [patent_app_number] => 11/241804 [patent_app_country] => US [patent_app_date] => 2005-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4254 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/525/07525130.pdf [firstpage_image] =>[orig_patent_app_number] => 11241804 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/241804
Polarization-doped field effect transistors (POLFETS) and materials and methods for making the same Sep 28, 2005 Issued
Array ( [id] => 366542 [patent_doc_number] => 07479421 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-20 [patent_title] => 'Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby' [patent_app_type] => utility [patent_app_number] => 11/238444 [patent_app_country] => US [patent_app_date] => 2005-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 5295 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/479/07479421.pdf [firstpage_image] =>[orig_patent_app_number] => 11238444 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/238444
Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby Sep 27, 2005 Issued
Array ( [id] => 5898270 [patent_doc_number] => 20060043503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Semiconductor constructions' [patent_app_type] => utility [patent_app_number] => 11/237396 [patent_app_country] => US [patent_app_date] => 2005-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4190 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20060043503.pdf [firstpage_image] =>[orig_patent_app_number] => 11237396 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/237396
Semiconductor constructions Sep 27, 2005 Issued
Array ( [id] => 7599554 [patent_doc_number] => 07582893 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-01 [patent_title] => 'Semiconductor memory device comprising one or more injecting bilayer electrodes' [patent_app_type] => utility [patent_app_number] => 11/227603 [patent_app_country] => US [patent_app_date] => 2005-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 11829 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/582/07582893.pdf [firstpage_image] =>[orig_patent_app_number] => 11227603 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/227603
Semiconductor memory device comprising one or more injecting bilayer electrodes Sep 14, 2005 Issued
Array ( [id] => 5790988 [patent_doc_number] => 20060012039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-19 [patent_title] => 'Methods of processing thick ILD layers using spray coating or lamination for C4 wafer level thick metal integrated flow' [patent_app_type] => utility [patent_app_number] => 11/221453 [patent_app_country] => US [patent_app_date] => 2005-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 4747 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20060012039.pdf [firstpage_image] =>[orig_patent_app_number] => 11221453 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/221453
Methods of processing thick ILD layers using spray coating or lamination for C4 wafer level thick metal integrated flow Sep 6, 2005 Abandoned
Array ( [id] => 646320 [patent_doc_number] => 07119386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-10 [patent_title] => 'Versatile system for triple-gated transistors with engineered corners' [patent_app_type] => utility [patent_app_number] => 11/221103 [patent_app_country] => US [patent_app_date] => 2005-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3727 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/119/07119386.pdf [firstpage_image] =>[orig_patent_app_number] => 11221103 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/221103
Versatile system for triple-gated transistors with engineered corners Sep 6, 2005 Issued
Array ( [id] => 547609 [patent_doc_number] => 07166900 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-01-23 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/205402 [patent_app_country] => US [patent_app_date] => 2005-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3455 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/166/07166900.pdf [firstpage_image] =>[orig_patent_app_number] => 11205402 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/205402
Semiconductor memory device Aug 16, 2005 Issued
Array ( [id] => 7228718 [patent_doc_number] => 20050269667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-08 [patent_title] => 'Process for manufacturing integrated resistor and phase-change memory element including this resistor' [patent_app_type] => utility [patent_app_number] => 11/201790 [patent_app_country] => US [patent_app_date] => 2005-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2274 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0269/20050269667.pdf [firstpage_image] =>[orig_patent_app_number] => 11201790 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/201790
Process for manufacturing integrated resistor and phase-change memory element including this resistor Aug 10, 2005 Abandoned
Array ( [id] => 5823758 [patent_doc_number] => 20060060940 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-23 [patent_title] => 'Rectifying charge storage element' [patent_app_type] => utility [patent_app_number] => 11/193067 [patent_app_country] => US [patent_app_date] => 2005-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6197 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20060060940.pdf [firstpage_image] =>[orig_patent_app_number] => 11193067 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/193067
Rectifying charge storage element Jul 27, 2005 Issued
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