Search

Barbara J Bullock

Examiner (ID: 9881)

Most Active Art Unit
2901
Art Unit(s)
2900, 2912, 2901, 2902
Total Applications
4468
Issued Applications
4372
Pending Applications
0
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 742962 [patent_doc_number] => 07030487 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-18 [patent_title] => 'Chip scale packaging with improved heat dissipation capability' [patent_app_type] => utility [patent_app_number] => 10/908633 [patent_app_country] => US [patent_app_date] => 2005-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1631 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/030/07030487.pdf [firstpage_image] =>[orig_patent_app_number] => 10908633 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/908633
Chip scale packaging with improved heat dissipation capability May 19, 2005 Issued
Array ( [id] => 547773 [patent_doc_number] => 07166913 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-23 [patent_title] => 'Heat dissipation for heat generating element of semiconductor device and related method' [patent_app_type] => utility [patent_app_number] => 10/907873 [patent_app_country] => US [patent_app_date] => 2005-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1768 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/166/07166913.pdf [firstpage_image] =>[orig_patent_app_number] => 10907873 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/907873
Heat dissipation for heat generating element of semiconductor device and related method Apr 18, 2005 Issued
Array ( [id] => 826809 [patent_doc_number] => 07402473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-22 [patent_title] => 'Semiconductor device and process for producing the same' [patent_app_type] => utility [patent_app_number] => 11/108827 [patent_app_country] => US [patent_app_date] => 2005-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 85 [patent_no_of_words] => 18824 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/402/07402473.pdf [firstpage_image] =>[orig_patent_app_number] => 11108827 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/108827
Semiconductor device and process for producing the same Apr 18, 2005 Issued
Array ( [id] => 7183487 [patent_doc_number] => 20050161812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'WAFER-LEVEL PACKAGE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 10/907744 [patent_app_country] => US [patent_app_date] => 2005-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3015 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20050161812.pdf [firstpage_image] =>[orig_patent_app_number] => 10907744 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/907744
WAFER-LEVEL PACKAGE STRUCTURE Apr 13, 2005 Abandoned
Array ( [id] => 7043352 [patent_doc_number] => 20050247947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-10 [patent_title] => 'High density LED array' [patent_app_type] => utility [patent_app_number] => 11/104954 [patent_app_country] => US [patent_app_date] => 2005-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7106 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0247/20050247947.pdf [firstpage_image] =>[orig_patent_app_number] => 11104954 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/104954
High density LED array Apr 11, 2005 Issued
Array ( [id] => 4782548 [patent_doc_number] => 20080135877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'Semiconductor Manufacturing Method and Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 11/568404 [patent_app_country] => US [patent_app_date] => 2005-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10376 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20080135877.pdf [firstpage_image] =>[orig_patent_app_number] => 11568404 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/568404
Semiconductor manufacturing method and semiconductor device Apr 10, 2005 Issued
Array ( [id] => 7002388 [patent_doc_number] => 20050167701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Method for fabrication of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/097168 [patent_app_country] => US [patent_app_date] => 2005-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 8208 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20050167701.pdf [firstpage_image] =>[orig_patent_app_number] => 11097168 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/097168
Method for fabrication of semiconductor device Apr 3, 2005 Abandoned
Array ( [id] => 380330 [patent_doc_number] => 07309906 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-12-18 [patent_title] => 'Apparatus and methods for providing highly effective and area efficient decoupling capacitance in programmable logic devices' [patent_app_type] => utility [patent_app_number] => 11/097503 [patent_app_country] => US [patent_app_date] => 2005-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2966 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/309/07309906.pdf [firstpage_image] =>[orig_patent_app_number] => 11097503 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/097503
Apparatus and methods for providing highly effective and area efficient decoupling capacitance in programmable logic devices Mar 31, 2005 Issued
Array ( [id] => 449717 [patent_doc_number] => 07250632 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-31 [patent_title] => 'Electronic devices having a layer overlying an edge of a different layer and a process for forming the same' [patent_app_type] => utility [patent_app_number] => 11/088164 [patent_app_country] => US [patent_app_date] => 2005-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 12909 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/250/07250632.pdf [firstpage_image] =>[orig_patent_app_number] => 11088164 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/088164
Electronic devices having a layer overlying an edge of a different layer and a process for forming the same Mar 22, 2005 Issued
Array ( [id] => 5817920 [patent_doc_number] => 20060022233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'CMOS imager with selectively silicided gates' [patent_app_type] => utility [patent_app_number] => 11/078709 [patent_app_country] => US [patent_app_date] => 2005-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7466 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20060022233.pdf [firstpage_image] =>[orig_patent_app_number] => 11078709 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/078709
CMOS imager with selectively silicided gates Mar 13, 2005 Issued
Array ( [id] => 4496288 [patent_doc_number] => 07956459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-07 [patent_title] => 'Semiconductor device and method of assembly' [patent_app_type] => utility [patent_app_number] => 11/816551 [patent_app_country] => US [patent_app_date] => 2005-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6514 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/956/07956459.pdf [firstpage_image] =>[orig_patent_app_number] => 11816551 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/816551
Semiconductor device and method of assembly Feb 27, 2005 Issued
Array ( [id] => 383343 [patent_doc_number] => 07307295 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-11 [patent_title] => 'Method and an apparatus for a hard-coded bit value changeable in any layer of metal' [patent_app_type] => utility [patent_app_number] => 11/049524 [patent_app_country] => US [patent_app_date] => 2005-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4088 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/307/07307295.pdf [firstpage_image] =>[orig_patent_app_number] => 11049524 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/049524
Method and an apparatus for a hard-coded bit value changeable in any layer of metal Jan 31, 2005 Issued
Array ( [id] => 5810882 [patent_doc_number] => 20060081990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-20 [patent_title] => 'CIRCUIT STRUCTURE' [patent_app_type] => utility [patent_app_number] => 10/905803 [patent_app_country] => US [patent_app_date] => 2005-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2779 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20060081990.pdf [firstpage_image] =>[orig_patent_app_number] => 10905803 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/905803
Circuit structure of package substrate Jan 20, 2005 Issued
Array ( [id] => 616806 [patent_doc_number] => 07145219 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-05 [patent_title] => 'Vertical integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/020753 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 100 [patent_no_of_words] => 24937 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/145/07145219.pdf [firstpage_image] =>[orig_patent_app_number] => 11020753 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/020753
Vertical integrated circuits Dec 22, 2004 Issued
Array ( [id] => 485391 [patent_doc_number] => 07217589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-15 [patent_title] => 'Deep photodiode isolation process' [patent_app_type] => utility [patent_app_number] => 11/009006 [patent_app_country] => US [patent_app_date] => 2004-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 6488 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/217/07217589.pdf [firstpage_image] =>[orig_patent_app_number] => 11009006 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/009006
Deep photodiode isolation process Dec 12, 2004 Issued
Array ( [id] => 390611 [patent_doc_number] => 07301207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-27 [patent_title] => 'Semiconductor device capable of threshold voltage adjustment by applying an external voltage' [patent_app_type] => utility [patent_app_number] => 11/008363 [patent_app_country] => US [patent_app_date] => 2004-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2974 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/301/07301207.pdf [firstpage_image] =>[orig_patent_app_number] => 11008363 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/008363
Semiconductor device capable of threshold voltage adjustment by applying an external voltage Dec 8, 2004 Issued
Array ( [id] => 5239825 [patent_doc_number] => 20070018316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'Electrode, method for producing same and semiconductor device using same' [patent_app_type] => utility [patent_app_number] => 10/574933 [patent_app_country] => US [patent_app_date] => 2004-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10033 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20070018316.pdf [firstpage_image] =>[orig_patent_app_number] => 10574933 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/574933
Electrode, method for producing same and semiconductor device using same Dec 5, 2004 Issued
Array ( [id] => 5838192 [patent_doc_number] => 20060118850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'COLLARLESS TRENCH DRAM DEVICE' [patent_app_type] => utility [patent_app_number] => 10/904933 [patent_app_country] => US [patent_app_date] => 2004-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4901 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20060118850.pdf [firstpage_image] =>[orig_patent_app_number] => 10904933 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/904933
Collarless trench DRAM device Dec 5, 2004 Issued
Array ( [id] => 6915601 [patent_doc_number] => 20050093162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Method to increase electromigration resistance of copper using self-assembled organic thiolate monolayers' [patent_app_type] => utility [patent_app_number] => 10/997536 [patent_app_country] => US [patent_app_date] => 2004-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3862 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20050093162.pdf [firstpage_image] =>[orig_patent_app_number] => 10997536 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/997536
Method to increase electromigration resistance of copper using self-assembled organic thiolate monolayers Nov 22, 2004 Issued
Array ( [id] => 5180764 [patent_doc_number] => 20070052106 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-08 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 10/976914 [patent_app_country] => US [patent_app_date] => 2004-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7780 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20070052106.pdf [firstpage_image] =>[orig_patent_app_number] => 10976914 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/976914
Semiconductor device and method for fabricating the same Oct 31, 2004 Abandoned
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