Barbara J Bullock
Examiner (ID: 9881)
Most Active Art Unit | 2901 |
Art Unit(s) | 2900, 2912, 2901, 2902 |
Total Applications | 4468 |
Issued Applications | 4372 |
Pending Applications | 0 |
Abandoned Applications | 96 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 742962
[patent_doc_number] => 07030487
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[patent_kind] => B1
[patent_issue_date] => 2006-04-18
[patent_title] => 'Chip scale packaging with improved heat dissipation capability'
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[patent_app_number] => 10/908633
[patent_app_country] => US
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[pdf_file] => patents/07/030/07030487.pdf
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Array
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[patent_issue_date] => 2007-01-23
[patent_title] => 'Heat dissipation for heat generating element of semiconductor device and related method'
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Array
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[patent_issue_date] => 2008-07-22
[patent_title] => 'Semiconductor device and process for producing the same'
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Array
(
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[patent_title] => 'WAFER-LEVEL PACKAGE STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 10/907744
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/907744 | WAFER-LEVEL PACKAGE STRUCTURE | Apr 13, 2005 | Abandoned |
Array
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[patent_title] => 'High density LED array'
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Array
(
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[patent_title] => 'Semiconductor Manufacturing Method and Semiconductor Device'
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/097168 | Method for fabrication of semiconductor device | Apr 3, 2005 | Abandoned |
Array
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[patent_title] => 'Apparatus and methods for providing highly effective and area efficient decoupling capacitance in programmable logic devices'
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[patent_app_number] => 11/097503
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Array
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[id] => 449717
[patent_doc_number] => 07250632
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[patent_issue_date] => 2007-07-31
[patent_title] => 'Electronic devices having a layer overlying an edge of a different layer and a process for forming the same'
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Array
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[id] => 5817920
[patent_doc_number] => 20060022233
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[patent_title] => 'CMOS imager with selectively silicided gates'
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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