Search

Barbara J Bullock

Examiner (ID: 9881)

Most Active Art Unit
2901
Art Unit(s)
2900, 2912, 2901, 2902
Total Applications
4468
Issued Applications
4372
Pending Applications
0
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9273418 [patent_doc_number] => 08637350 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-28 [patent_title] => 'Method of manufacturing chip-stacked semiconductor package' [patent_app_type] => utility [patent_app_number] => 13/439447 [patent_app_country] => US [patent_app_date] => 2012-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 35 [patent_no_of_words] => 11749 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13439447 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/439447
Method of manufacturing chip-stacked semiconductor package Apr 3, 2012 Issued
Array ( [id] => 8932519 [patent_doc_number] => 08492218 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-07-23 [patent_title] => 'Removal of an overlap of dual stress liners' [patent_app_type] => utility [patent_app_number] => 13/438422 [patent_app_country] => US [patent_app_date] => 2012-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5841 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13438422 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/438422
Removal of an overlap of dual stress liners Apr 2, 2012 Issued
Array ( [id] => 9286718 [patent_doc_number] => 08643048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-04 [patent_title] => 'Light emitting device' [patent_app_type] => utility [patent_app_number] => 13/434299 [patent_app_country] => US [patent_app_date] => 2012-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 28 [patent_no_of_words] => 12148 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13434299 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/434299
Light emitting device Mar 28, 2012 Issued
Array ( [id] => 8390773 [patent_doc_number] => 20120228614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-13 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/413854 [patent_app_country] => US [patent_app_date] => 2012-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8813 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13413854 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/413854
Semiconductor device and manufacturing method thereof Mar 6, 2012 Issued
Array ( [id] => 8390847 [patent_doc_number] => 20120228687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-13 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/410608 [patent_app_country] => US [patent_app_date] => 2012-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8098 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13410608 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/410608
Semiconductor memory device Mar 1, 2012 Issued
Array ( [id] => 8261906 [patent_doc_number] => 20120161334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-28 [patent_title] => 'REDUNDANCY DESIGN WITH ELECTRO-MIGRATION IMMUNITY AND METHOD OF MANUFACTURE' [patent_app_type] => utility [patent_app_number] => 13/400900 [patent_app_country] => US [patent_app_date] => 2012-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3729 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13400900 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/400900
Redundancy design with electro-migration immunity and method of manufacture Feb 20, 2012 Issued
Array ( [id] => 8198554 [patent_doc_number] => 20120122295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'SEMICONDUCTOR DEVICE WITH RECESS AND FIN STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/360194 [patent_app_country] => US [patent_app_date] => 2012-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3839 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20120122295.pdf [firstpage_image] =>[orig_patent_app_number] => 13360194 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/360194
Method of manufacturing semiconductor device with recess and Fin structure Jan 26, 2012 Issued
Array ( [id] => 8180138 [patent_doc_number] => 20120112285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-10 [patent_title] => 'SOI CMOS CIRCUITS WITH SUBSTRATE BIAS' [patent_app_type] => utility [patent_app_number] => 13/344006 [patent_app_country] => US [patent_app_date] => 2012-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4133 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20120112285.pdf [firstpage_image] =>[orig_patent_app_number] => 13344006 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/344006
SOI CMOS circuits with substrate bias Jan 4, 2012 Issued
Array ( [id] => 8680785 [patent_doc_number] => 20130049069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-28 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/577443 [patent_app_country] => US [patent_app_date] => 2011-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5666 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13577443 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/577443
Semiconductor device and method for manufacturing the same Nov 24, 2011 Issued
Array ( [id] => 8792197 [patent_doc_number] => 20130109166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-02 [patent_title] => 'METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH CONTROLLED P-CHANNEL THRESHOLD VOLTAGE' [patent_app_type] => utility [patent_app_number] => 13/286292 [patent_app_country] => US [patent_app_date] => 2011-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2398 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13286292 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/286292
Methods for fabricating integrated circuits with controlled P-channel threshold voltage Oct 31, 2011 Issued
Array ( [id] => 8792167 [patent_doc_number] => 20130109136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-02 [patent_title] => 'METHODS OF FABRICATING ELECTRONICS ASSEMBLIES' [patent_app_type] => utility [patent_app_number] => 13/285547 [patent_app_country] => US [patent_app_date] => 2011-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5370 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13285547 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/285547
Methods of fabricating electronics assemblies Oct 30, 2011 Issued
Array ( [id] => 8469717 [patent_doc_number] => 08298895 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-10-30 [patent_title] => 'Selective threshold voltage implants for long channel devices' [patent_app_type] => utility [patent_app_number] => 13/285282 [patent_app_country] => US [patent_app_date] => 2011-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3510 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13285282 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/285282
Selective threshold voltage implants for long channel devices Oct 30, 2011 Issued
Array ( [id] => 8664312 [patent_doc_number] => 08377773 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-02-19 [patent_title] => 'Transistors having a channel semiconductor alloy formed in an early process stage based on a hard mask' [patent_app_type] => utility [patent_app_number] => 13/285600 [patent_app_country] => US [patent_app_date] => 2011-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 26 [patent_no_of_words] => 10792 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13285600 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/285600
Transistors having a channel semiconductor alloy formed in an early process stage based on a hard mask Oct 30, 2011 Issued
Array ( [id] => 8788942 [patent_doc_number] => 20130105912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-02 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/283603 [patent_app_country] => US [patent_app_date] => 2011-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3170 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13283603 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/283603
Semiconductor device Oct 27, 2011 Issued
Array ( [id] => 8414224 [patent_doc_number] => 20120241724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-27 [patent_title] => 'LIGHT EMITTING CHIP' [patent_app_type] => utility [patent_app_number] => 13/283610 [patent_app_country] => US [patent_app_date] => 2011-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1466 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13283610 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/283610
Light emitting chip Oct 27, 2011 Issued
Array ( [id] => 8227943 [patent_doc_number] => 20120142148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'METHOD OF MANUFACTURING HIGH FREQUENCY DEVICE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 13/283626 [patent_app_country] => US [patent_app_date] => 2011-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3681 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13283626 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/283626
Method of manufacturing high frequency device structure Oct 27, 2011 Issued
Array ( [id] => 8180130 [patent_doc_number] => 20120112277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-10 [patent_title] => 'INTEGRATED LATERAL HIGH VOLTAGE MOSFET' [patent_app_type] => utility [patent_app_number] => 13/284011 [patent_app_country] => US [patent_app_date] => 2011-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5478 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20120112277.pdf [firstpage_image] =>[orig_patent_app_number] => 13284011 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/284011
Integrated lateral high voltage MOSFET Oct 27, 2011 Issued
Array ( [id] => 8224738 [patent_doc_number] => 20120138947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'Epitaxial Structure With An Epitaxial Defect Barrier Layer And Methods Making The Same' [patent_app_type] => utility [patent_app_number] => 13/283309 [patent_app_country] => US [patent_app_date] => 2011-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4567 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13283309 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/283309
Epitaxial structure with an epitaxial defect barrier layer Oct 26, 2011 Issued
Array ( [id] => 8689824 [patent_doc_number] => 08389351 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-05 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/282812 [patent_app_country] => US [patent_app_date] => 2011-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 52 [patent_no_of_words] => 9780 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13282812 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/282812
Method for fabricating semiconductor device Oct 26, 2011 Issued
Array ( [id] => 8166074 [patent_doc_number] => 20120104411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'TEXTURED III-V SEMICONDUCTOR' [patent_app_type] => utility [patent_app_number] => 13/283211 [patent_app_country] => US [patent_app_date] => 2011-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5136 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20120104411.pdf [firstpage_image] =>[orig_patent_app_number] => 13283211 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/283211
TEXTURED III-V SEMICONDUCTOR Oct 26, 2011 Abandoned
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