Search

Barbara J Bullock

Examiner (ID: 9881)

Most Active Art Unit
2901
Art Unit(s)
2900, 2912, 2901, 2902
Total Applications
4468
Issued Applications
4372
Pending Applications
0
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7101454 [patent_doc_number] => 20050104180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Electronic device with reduced entrapment of material between die and substrate electrical connections' [patent_app_type] => utility [patent_app_number] => 10/706963 [patent_app_country] => US [patent_app_date] => 2003-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3441 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20050104180.pdf [firstpage_image] =>[orig_patent_app_number] => 10706963 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/706963
Electronic device with reduced entrapment of material between die and substrate electrical connections Nov 13, 2003 Abandoned
Array ( [id] => 638351 [patent_doc_number] => 07126208 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-24 [patent_title] => 'Composition for forming porous film, porous film and method for forming the same, interlevel insulator film, and semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/706863 [patent_app_country] => US [patent_app_date] => 2003-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 8361 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/126/07126208.pdf [firstpage_image] =>[orig_patent_app_number] => 10706863 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/706863
Composition for forming porous film, porous film and method for forming the same, interlevel insulator film, and semiconductor device Nov 11, 2003 Issued
Array ( [id] => 7191451 [patent_doc_number] => 20050040495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'Horizontal current bipolar transistor and fabrication method' [patent_app_type] => utility [patent_app_number] => 10/677643 [patent_app_country] => US [patent_app_date] => 2003-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4264 [patent_no_of_claims] => 91 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20050040495.pdf [firstpage_image] =>[orig_patent_app_number] => 10677643 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/677643
Horizontal current bipolar transistor and fabrication method Sep 30, 2003 Issued
Array ( [id] => 7198255 [patent_doc_number] => 20050051798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Silicon germanium heterojunction bipolar transistor with carbon incorporation' [patent_app_type] => utility [patent_app_number] => 10/660048 [patent_app_country] => US [patent_app_date] => 2003-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7123 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20050051798.pdf [firstpage_image] =>[orig_patent_app_number] => 10660048 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/660048
Silicon germanium heterojunction bipolar transistor with carbon incorporation Sep 10, 2003 Issued
Array ( [id] => 1002708 [patent_doc_number] => 06909165 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-21 [patent_title] => 'Obverse/reverse discriminative rectangular nitride semiconductor wafer' [patent_app_type] => utility [patent_app_number] => 10/658378 [patent_app_country] => US [patent_app_date] => 2003-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 8363 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/909/06909165.pdf [firstpage_image] =>[orig_patent_app_number] => 10658378 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/658378
Obverse/reverse discriminative rectangular nitride semiconductor wafer Sep 9, 2003 Issued
Array ( [id] => 7030908 [patent_doc_number] => 20050029581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-10 [patent_title] => 'Field-effect-controllable semiconductor component and method for producing the semiconductor component' [patent_app_type] => utility [patent_app_number] => 10/654683 [patent_app_country] => US [patent_app_date] => 2003-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8989 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20050029581.pdf [firstpage_image] =>[orig_patent_app_number] => 10654683 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/654683
Field-effect-controllable semiconductor component and method for producing the semiconductor component Sep 3, 2003 Issued
Array ( [id] => 7394765 [patent_doc_number] => 20040038441 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Thin film transistor and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/640299 [patent_app_country] => US [patent_app_date] => 2003-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11672 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20040038441.pdf [firstpage_image] =>[orig_patent_app_number] => 10640299 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/640299
Thin film transistor and method of manufacturing the same Aug 13, 2003 Issued
Array ( [id] => 7471759 [patent_doc_number] => 20040121607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'Method of producing a semiconductor integrated circuit device and the semiconductor integrated circuit device' [patent_app_type] => new [patent_app_number] => 10/626768 [patent_app_country] => US [patent_app_date] => 2003-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 51 [patent_no_of_words] => 15687 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20040121607.pdf [firstpage_image] =>[orig_patent_app_number] => 10626768 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/626768
Method of producing a semiconductor integrated circuit device and the semiconductor integrated circuit device Jul 24, 2003 Issued
Array ( [id] => 7365405 [patent_doc_number] => 20040092131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'Method for depositing a fluorine-doped silica film' [patent_app_type] => new [patent_app_number] => 10/343508 [patent_app_country] => US [patent_app_date] => 2003-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2320 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20040092131.pdf [firstpage_image] =>[orig_patent_app_number] => 10343508 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/343508
Method for depositing a fluorine-doped silica film Jul 24, 2003 Issued
Array ( [id] => 979332 [patent_doc_number] => 06930337 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-16 [patent_title] => 'CMOS imager with selectively silicided gate' [patent_app_type] => utility [patent_app_number] => 10/617706 [patent_app_country] => US [patent_app_date] => 2003-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 7543 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/930/06930337.pdf [firstpage_image] =>[orig_patent_app_number] => 10617706 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/617706
CMOS imager with selectively silicided gate Jul 13, 2003 Issued
Array ( [id] => 7603192 [patent_doc_number] => 07235842 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-26 [patent_title] => 'Insulated gate power semiconductor devices' [patent_app_type] => utility [patent_app_number] => 10/564214 [patent_app_country] => US [patent_app_date] => 2003-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 59 [patent_no_of_words] => 12482 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/235/07235842.pdf [firstpage_image] =>[orig_patent_app_number] => 10564214 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/564214
Insulated gate power semiconductor devices Jul 11, 2003 Issued
Array ( [id] => 1141467 [patent_doc_number] => 06777299 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-17 [patent_title] => 'Method for removal of a spacer' [patent_app_type] => B1 [patent_app_number] => 10/614388 [patent_app_country] => US [patent_app_date] => 2003-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 3977 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/777/06777299.pdf [firstpage_image] =>[orig_patent_app_number] => 10614388 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/614388
Method for removal of a spacer Jul 6, 2003 Issued
Array ( [id] => 793406 [patent_doc_number] => 06982452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-03 [patent_title] => 'Rectifying charge storage element' [patent_app_type] => utility [patent_app_number] => 10/895434 [patent_app_country] => US [patent_app_date] => 2003-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 6194 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/982/06982452.pdf [firstpage_image] =>[orig_patent_app_number] => 10895434 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/895434
Rectifying charge storage element Jun 30, 2003 Issued
Array ( [id] => 1040575 [patent_doc_number] => 06869873 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-22 [patent_title] => 'Copper silicide passivation for improved reliability' [patent_app_type] => utility [patent_app_number] => 10/609889 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 5121 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/869/06869873.pdf [firstpage_image] =>[orig_patent_app_number] => 10609889 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/609889
Copper silicide passivation for improved reliability Jun 29, 2003 Issued
Array ( [id] => 1138310 [patent_doc_number] => 06780736 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-24 [patent_title] => 'Method for image reversal of implant resist using a single photolithography exposure and structures formed thereby' [patent_app_type] => B1 [patent_app_number] => 10/604009 [patent_app_country] => US [patent_app_date] => 2003-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 3271 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/780/06780736.pdf [firstpage_image] =>[orig_patent_app_number] => 10604009 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/604009
Method for image reversal of implant resist using a single photolithography exposure and structures formed thereby Jun 19, 2003 Issued
Array ( [id] => 7349033 [patent_doc_number] => 20040248365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-09 [patent_title] => 'AREA-EFFICIENT STACK CAPACITOR' [patent_app_type] => new [patent_app_number] => 10/456648 [patent_app_country] => US [patent_app_date] => 2003-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1893 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20040248365.pdf [firstpage_image] =>[orig_patent_app_number] => 10456648 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/456648
Area-efficient stack capacitor Jun 4, 2003 Issued
Array ( [id] => 1005358 [patent_doc_number] => 06905953 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-14 [patent_title] => 'Selective passivation of exposed silicon' [patent_app_type] => utility [patent_app_number] => 10/454254 [patent_app_country] => US [patent_app_date] => 2003-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4492 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/905/06905953.pdf [firstpage_image] =>[orig_patent_app_number] => 10454254 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/454254
Selective passivation of exposed silicon Jun 2, 2003 Issued
Array ( [id] => 522430 [patent_doc_number] => 07190052 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-13 [patent_title] => 'Semiconductor devices with oxide coatings selectively positioned over exposed features including semiconductor material' [patent_app_type] => utility [patent_app_number] => 10/454256 [patent_app_country] => US [patent_app_date] => 2003-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4481 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/190/07190052.pdf [firstpage_image] =>[orig_patent_app_number] => 10454256 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/454256
Semiconductor devices with oxide coatings selectively positioned over exposed features including semiconductor material Jun 2, 2003 Issued
Array ( [id] => 6664267 [patent_doc_number] => 20030203593 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-30 [patent_title] => 'PD-SOI substrate with suppressed floating body effect and method for its fabrication' [patent_app_type] => new [patent_app_number] => 10/443023 [patent_app_country] => US [patent_app_date] => 2003-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4099 [patent_no_of_claims] => 93 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20030203593.pdf [firstpage_image] =>[orig_patent_app_number] => 10443023 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/443023
PD-SOI substrate with suppressed floating body effect and method for its fabrication May 21, 2003 Issued
Array ( [id] => 1210909 [patent_doc_number] => 06713835 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'Method for manufacturing a multi-level interconnect structure' [patent_app_type] => B1 [patent_app_number] => 10/443709 [patent_app_country] => US [patent_app_date] => 2003-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 5664 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/713/06713835.pdf [firstpage_image] =>[orig_patent_app_number] => 10443709 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/443709
Method for manufacturing a multi-level interconnect structure May 21, 2003 Issued
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