Barbara J Bullock

Array ( [id] => 6655960 [patent_doc_number] => 20030132492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-17 [patent_title] => ' PROCESS FOR PASSIVATING THE SEMICONDUCTOR-DIELECTRIC INTERFACE OF A MOS DEVICE AND MOS DEVICE FORMED THEREBY\n ' [patent_app_type] => new-utility [patent_app_number] => 10/249184 [patent_app_country] => US [patent_app_date] => 2003-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3901 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20030132492.pdf [firstpage_image] =>[orig_patent_app_number] => 10249184 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1138229 [patent_doc_number] => 06780716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-24 [patent_title] => 'Chip differentiation at the level of a reticle' [patent_app_type] => B2 [patent_app_number] => 10/393049 [patent_app_country] => US [patent_app_date] => 2003-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 3647 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/780/06780716.pdf [firstpage_image] =>[orig_patent_app_number] => 10393049 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1056761 [patent_doc_number] => 06855951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-15 [patent_title] => 'Fluorinated polythiophenes and devices thereof' [patent_app_type] => utility [patent_app_number] => 10/392639 [patent_app_country] => US [patent_app_date] => 2003-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 6801 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 8 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/855/06855951.pdf [firstpage_image] =>[orig_patent_app_number] => 10392639 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6711185 [patent_doc_number] => 20030170934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-11 [patent_title] => 'Top layers of metal for high performance IC\'s' [patent_app_type] => new [patent_app_number] => 10/389543 [patent_app_country] => US [patent_app_date] => 2003-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5247 [patent_no_of_claims] => 79 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20030170934.pdf [firstpage_image] =>[orig_patent_app_number] => 10389543 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7375220 [patent_doc_number] => 20040178415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'LIGHT-EMITTING DIODE WITH ENHANCED BRIGHTNESS AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => new [patent_app_number] => 10/384619 [patent_app_country] => US [patent_app_date] => 2003-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2845 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20040178415.pdf [firstpage_image] =>[orig_patent_app_number] => 10384619 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6834820 [patent_doc_number] => 20030162366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-28 [patent_title] => 'Integrated circuit isolation system' [patent_app_type] => new [patent_app_number] => 10/383031 [patent_app_country] => US [patent_app_date] => 2003-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5282 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20030162366.pdf [firstpage_image] =>[orig_patent_app_number] => 10383031 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6841121 [patent_doc_number] => 20030146468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-07 [patent_title] => 'Bipolar transistor manufacturing method' [patent_app_type] => new [patent_app_number] => 10/379169 [patent_app_country] => US [patent_app_date] => 2003-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4249 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20030146468.pdf [firstpage_image] =>[orig_patent_app_number] => 10379169 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6704345 [patent_doc_number] => 20030151079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-14 [patent_title] => 'Self-aligned magnetic clad write line and its method of formation' [patent_app_type] => new [patent_app_number] => 10/378348 [patent_app_country] => US [patent_app_date] => 2003-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5545 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20030151079.pdf [firstpage_image] =>[orig_patent_app_number] => 10378348 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1197763 [patent_doc_number] => 06727546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-27 [patent_title] => 'Self-aligned triple gate silicon-on-insulator (SOI) device' [patent_app_type] => B2 [patent_app_number] => 10/379239 [patent_app_country] => US [patent_app_date] => 2003-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 44 [patent_no_of_words] => 3372 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/727/06727546.pdf [firstpage_image] =>[orig_patent_app_number] => 10379239 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6820054 [patent_doc_number] => 20030218215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-27 [patent_title] => 'Process for fabricating semiconductor device' [patent_app_type] => new [patent_app_number] => 10/373878 [patent_app_country] => US [patent_app_date] => 2003-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7006 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20030218215.pdf [firstpage_image] =>[orig_patent_app_number] => 10373878 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1141381 [patent_doc_number] => 06777278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-17 [patent_title] => 'Methods of fabricating aluminum gallium nitride/gallium nitride high electron mobility transistors having a gate contact on a gallium nitride based cap segment' [patent_app_type] => B2 [patent_app_number] => 10/374438 [patent_app_country] => US [patent_app_date] => 2003-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 0 [patent_no_of_words] => 4723 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/777/06777278.pdf [firstpage_image] =>[orig_patent_app_number] => 10374438 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6659680 [patent_doc_number] => 20030134470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-17 [patent_title] => 'Layer structure having contact hole, fin-shaped capacitor using the layer structure, method of producing the fin-shaped capacitor, and dynamic random access memory having the fin-shaped capacitor' [patent_app_type] => new [patent_app_number] => 10/354088 [patent_app_country] => US [patent_app_date] => 2003-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 11078 [patent_no_of_claims] => 73 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20030134470.pdf [firstpage_image] =>[orig_patent_app_number] => 10354088 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6834801 [patent_doc_number] => 20030162347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-28 [patent_title] => 'Self aligned method of forming a semiconductor memory array of floating gate memory cells with control gate protruding portions' [patent_app_type] => new [patent_app_number] => 10/356783 [patent_app_country] => US [patent_app_date] => 2003-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11156 [patent_no_of_claims] => 70 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20030162347.pdf [firstpage_image] =>[orig_patent_app_number] => 10356783 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6833650 [patent_doc_number] => 20030161195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-28 [patent_title] => 'Integrated resistor, phase-change memory element including this resistor, and process for the fabrication thereof' [patent_app_type] => new [patent_app_number] => 10/345129 [patent_app_country] => US [patent_app_date] => 2003-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2310 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20030161195.pdf [firstpage_image] =>[orig_patent_app_number] => 10345129 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6645502 [patent_doc_number] => 20030104289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-05 [patent_title] => 'Photomask and pattern forming method used in a thermal flow process and semiconductor integrated circuit fabricated using the thermal flow process' [patent_app_type] => new [patent_app_number] => 10/341159 [patent_app_country] => US [patent_app_date] => 2003-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5295 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20030104289.pdf [firstpage_image] =>[orig_patent_app_number] => 10341159 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1134402 [patent_doc_number] => 06784089 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-31 [patent_title] => 'Flat-top bumping structure and preparation method' [patent_app_type] => B2 [patent_app_number] => 10/342220 [patent_app_country] => US [patent_app_date] => 2003-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 28 [patent_no_of_words] => 5508 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/784/06784089.pdf [firstpage_image] =>[orig_patent_app_number] => 10342220 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1261487 [patent_doc_number] => 06664170 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-16 [patent_title] => 'Method for forming device isolation layer of a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 10/341173 [patent_app_country] => US [patent_app_date] => 2003-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 2069 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/664/06664170.pdf [firstpage_image] =>[orig_patent_app_number] => 10341173 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6764111 [patent_doc_number] => 20030098509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-29 [patent_title] => 'Semiconductor device, semiconductor element and method for producing same' [patent_app_type] => new [patent_app_number] => 10/340750 [patent_app_country] => US [patent_app_date] => 2003-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 79 [patent_figures_cnt] => 79 [patent_no_of_words] => 17412 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20030098509.pdf [firstpage_image] =>[orig_patent_app_number] => 10340750 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7318781 [patent_doc_number] => 20040135141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Electrostatic Discharge Protection Networks For Triple Well Semiconductor Devices' [patent_app_type] => new [patent_app_number] => 10/248329 [patent_app_country] => US [patent_app_date] => 2003-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7282 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20040135141.pdf [firstpage_image] =>[orig_patent_app_number] => 10248329 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7335514 [patent_doc_number] => 20040132264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-08 [patent_title] => 'INTEGRATED HIGH PERFORMANCE MOS TUNNELING LED IN ULSI TECHNOLOGY' [patent_app_type] => new [patent_app_number] => 10/338138 [patent_app_country] => US [patent_app_date] => 2003-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3314 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20040132264.pdf [firstpage_image] =>[orig_patent_app_number] => 10338138 [rel_patent_id] =>[rel_patent_doc_number] =>)