Search

Barbara J Bullock

Examiner (ID: 9881)

Most Active Art Unit
2901
Art Unit(s)
2900, 2912, 2901, 2902
Total Applications
4468
Issued Applications
4372
Pending Applications
0
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6809209 [patent_doc_number] => 20030199148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Method of reducing the thickness of a silicon substrate' [patent_app_type] => new [patent_app_number] => 10/318529 [patent_app_country] => US [patent_app_date] => 2002-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1876 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20030199148.pdf [firstpage_image] =>[orig_patent_app_number] => 10318529 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/318529
Method of reducing the thickness of a silicon substrate Dec 12, 2002 Issued
Array ( [id] => 7396647 [patent_doc_number] => 20040104405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-03 [patent_title] => 'Novel CMOS device' [patent_app_type] => new [patent_app_number] => 10/307619 [patent_app_country] => US [patent_app_date] => 2002-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2368 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20040104405.pdf [firstpage_image] =>[orig_patent_app_number] => 10307619 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/307619
CMOS device Dec 1, 2002 Issued
Array ( [id] => 672933 [patent_doc_number] => 07091536 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-15 [patent_title] => 'Isolation process and structure for CMOS imagers' [patent_app_type] => utility [patent_app_number] => 10/293494 [patent_app_country] => US [patent_app_date] => 2002-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 6444 [patent_no_of_claims] => 94 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/091/07091536.pdf [firstpage_image] =>[orig_patent_app_number] => 10293494 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/293494
Isolation process and structure for CMOS imagers Nov 13, 2002 Issued
Array ( [id] => 6847167 [patent_doc_number] => 20030166334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-04 [patent_title] => 'Bond pad and process for fabricating the same' [patent_app_type] => new [patent_app_number] => 10/065630 [patent_app_country] => US [patent_app_date] => 2002-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3565 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20030166334.pdf [firstpage_image] =>[orig_patent_app_number] => 10065630 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/065630
Bond pad and process for fabricating the same Nov 4, 2002 Abandoned
Array ( [id] => 7634397 [patent_doc_number] => 06657223 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Strained silicon MOSFET having silicon source/drain regions and method for its fabrication' [patent_app_type] => B1 [patent_app_number] => 10/282538 [patent_app_country] => US [patent_app_date] => 2002-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3938 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/657/06657223.pdf [firstpage_image] =>[orig_patent_app_number] => 10282538 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/282538
Strained silicon MOSFET having silicon source/drain regions and method for its fabrication Oct 28, 2002 Issued
Array ( [id] => 6649628 [patent_doc_number] => 20030104668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-05 [patent_title] => 'Capacitor structure of semiconductor device and method for forming the same' [patent_app_type] => new [patent_app_number] => 10/279682 [patent_app_country] => US [patent_app_date] => 2002-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4034 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20030104668.pdf [firstpage_image] =>[orig_patent_app_number] => 10279682 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/279682
Capacitor structure of semiconductor device and method for forming the same Oct 23, 2002 Issued
Array ( [id] => 6664291 [patent_doc_number] => 20030203617 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-30 [patent_title] => 'Process of forming copper structures' [patent_app_type] => new [patent_app_number] => 10/279057 [patent_app_country] => US [patent_app_date] => 2002-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8309 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20030203617.pdf [firstpage_image] =>[orig_patent_app_number] => 10279057 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/279057
Process of forming copper structures Oct 23, 2002 Issued
Array ( [id] => 1205466 [patent_doc_number] => 06716682 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-06 [patent_title] => 'SOI CMOS device with reduced DIBL' [patent_app_type] => B1 [patent_app_number] => 10/268578 [patent_app_country] => US [patent_app_date] => 2002-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3741 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/716/06716682.pdf [firstpage_image] =>[orig_patent_app_number] => 10268578 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/268578
SOI CMOS device with reduced DIBL Oct 9, 2002 Issued
Array ( [id] => 7310109 [patent_doc_number] => 20040032003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-19 [patent_title] => 'Semiconductor device fabricated on surface of silicon having <110>direction of crystal plane and its production method' [patent_app_type] => new [patent_app_number] => 10/416969 [patent_app_country] => US [patent_app_date] => 2003-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6670 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20040032003.pdf [firstpage_image] =>[orig_patent_app_number] => 10416969 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/416969
Semiconductor device fabricated on surface of silicon having <110> direction of crystal plane and its production method Oct 1, 2002 Issued
Array ( [id] => 6750545 [patent_doc_number] => 20030045065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'Method of producing a semiconductor integrated circuit device and the semiconductor integrated circuit device' [patent_app_type] => new [patent_app_number] => 10/256027 [patent_app_country] => US [patent_app_date] => 2002-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 51 [patent_no_of_words] => 15676 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20030045065.pdf [firstpage_image] =>[orig_patent_app_number] => 10256027 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/256027
Method of producing a semiconductor integrated circuit device and the semiconductor integrated circuit device Sep 26, 2002 Abandoned
Array ( [id] => 7634835 [patent_doc_number] => 06656783 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-02 [patent_title] => 'Semiconductor device having shallow trench isolation structure and manufacturing method thereof' [patent_app_type] => B2 [patent_app_number] => 10/255526 [patent_app_country] => US [patent_app_date] => 2002-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 5275 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/656/06656783.pdf [firstpage_image] =>[orig_patent_app_number] => 10255526 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/255526
Semiconductor device having shallow trench isolation structure and manufacturing method thereof Sep 24, 2002 Issued
Array ( [id] => 1156334 [patent_doc_number] => 06762120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-13 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => B2 [patent_app_number] => 10/251975 [patent_app_country] => US [patent_app_date] => 2002-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 52 [patent_no_of_words] => 7990 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/762/06762120.pdf [firstpage_image] =>[orig_patent_app_number] => 10251975 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/251975
Semiconductor device and method for fabricating the same Sep 22, 2002 Issued
Array ( [id] => 6807316 [patent_doc_number] => 20030197255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Semiconductor device' [patent_app_type] => new [patent_app_number] => 10/247289 [patent_app_country] => US [patent_app_date] => 2002-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4170 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20030197255.pdf [firstpage_image] =>[orig_patent_app_number] => 10247289 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/247289
Semiconductor device Sep 19, 2002 Issued
Array ( [id] => 6671888 [patent_doc_number] => 20030057491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/246629 [patent_app_country] => US [patent_app_date] => 2002-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8800 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20030057491.pdf [firstpage_image] =>[orig_patent_app_number] => 10246629 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/246629
Semiconductor device and method of manufacturing the same Sep 18, 2002 Issued
Array ( [id] => 6772462 [patent_doc_number] => 20030015800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-23 [patent_title] => 'Semiconductor device having a multiple layer wiring structure, wiring method, wiring device, and recording medium' [patent_app_type] => new [patent_app_number] => 10/246633 [patent_app_country] => US [patent_app_date] => 2002-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7676 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20030015800.pdf [firstpage_image] =>[orig_patent_app_number] => 10246633 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/246633
Semiconductor device having a multiple layer wiring structure, wiring method, wiring device, and recording medium Sep 18, 2002 Abandoned
Array ( [id] => 7135200 [patent_doc_number] => 20040043598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'METHOD FOR CREATING A DAMASCENE INTERCONNECT USING A TWO-STEP ELECTROPLATING PROCESS' [patent_app_type] => new [patent_app_number] => 10/232684 [patent_app_country] => US [patent_app_date] => 2002-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3596 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20040043598.pdf [firstpage_image] =>[orig_patent_app_number] => 10232684 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/232684
Method for creating a damascene interconnect using a two-step electroplating process Sep 2, 2002 Issued
Array ( [id] => 7612435 [patent_doc_number] => 06903401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-07 [patent_title] => 'Semiconductor devices with conductive lines that are laterally offset relative to corresponding contacts' [patent_app_type] => utility [patent_app_number] => 10/230732 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 4953 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/903/06903401.pdf [firstpage_image] =>[orig_patent_app_number] => 10230732 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/230732
Semiconductor devices with conductive lines that are laterally offset relative to corresponding contacts Aug 28, 2002 Issued
Array ( [id] => 944105 [patent_doc_number] => 06967159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-22 [patent_title] => 'Systems and methods for forming refractory metal nitride layers using organic amines' [patent_app_type] => utility [patent_app_number] => 10/229743 [patent_app_country] => US [patent_app_date] => 2002-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 7706 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/967/06967159.pdf [firstpage_image] =>[orig_patent_app_number] => 10229743 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/229743
Systems and methods for forming refractory metal nitride layers using organic amines Aug 27, 2002 Issued
Array ( [id] => 6755936 [patent_doc_number] => 20030003713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/227284 [patent_app_country] => US [patent_app_date] => 2002-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 15315 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 22 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20030003713.pdf [firstpage_image] =>[orig_patent_app_number] => 10227284 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/227284
Semiconductor device and method for manufacturing the same Aug 25, 2002 Issued
Array ( [id] => 1050079 [patent_doc_number] => 06861356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-01 [patent_title] => 'Method of forming a barrier film and method of forming wiring structure and electrodes of semiconductor device having a barrier film' [patent_app_type] => utility [patent_app_number] => 10/225228 [patent_app_country] => US [patent_app_date] => 2002-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 30 [patent_no_of_words] => 15183 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 377 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/861/06861356.pdf [firstpage_image] =>[orig_patent_app_number] => 10225228 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/225228
Method of forming a barrier film and method of forming wiring structure and electrodes of semiconductor device having a barrier film Aug 21, 2002 Issued
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