Barbara J Bullock
Examiner (ID: 9881)
Most Active Art Unit | 2901 |
Art Unit(s) | 2900, 2912, 2901, 2902 |
Total Applications | 4468 |
Issued Applications | 4372 |
Pending Applications | 0 |
Abandoned Applications | 96 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 6809209
[patent_doc_number] => 20030199148
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-23
[patent_title] => 'Method of reducing the thickness of a silicon substrate'
[patent_app_type] => new
[patent_app_number] => 10/318529
[patent_app_country] => US
[patent_app_date] => 2002-12-13
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[pdf_file] => publications/A1/0199/20030199148.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/318529 | Method of reducing the thickness of a silicon substrate | Dec 12, 2002 | Issued |
Array
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[patent_doc_number] => 20040104405
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[patent_kind] => A1
[patent_issue_date] => 2004-06-03
[patent_title] => 'Novel CMOS device'
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[firstpage_image] =>[orig_patent_app_number] => 10307619
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/307619 | CMOS device | Dec 1, 2002 | Issued |
Array
(
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[patent_doc_number] => 07091536
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[patent_kind] => B2
[patent_issue_date] => 2006-08-15
[patent_title] => 'Isolation process and structure for CMOS imagers'
[patent_app_type] => utility
[patent_app_number] => 10/293494
[patent_app_country] => US
[patent_app_date] => 2002-11-14
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/293494 | Isolation process and structure for CMOS imagers | Nov 13, 2002 | Issued |
Array
(
[id] => 6847167
[patent_doc_number] => 20030166334
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[patent_kind] => A1
[patent_issue_date] => 2003-09-04
[patent_title] => 'Bond pad and process for fabricating the same'
[patent_app_type] => new
[patent_app_number] => 10/065630
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[patent_app_date] => 2002-11-05
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[firstpage_image] =>[orig_patent_app_number] => 10065630
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/065630 | Bond pad and process for fabricating the same | Nov 4, 2002 | Abandoned |
Array
(
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[patent_doc_number] => 06657223
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[patent_issue_date] => 2003-12-02
[patent_title] => 'Strained silicon MOSFET having silicon source/drain regions and method for its fabrication'
[patent_app_type] => B1
[patent_app_number] => 10/282538
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/282538 | Strained silicon MOSFET having silicon source/drain regions and method for its fabrication | Oct 28, 2002 | Issued |
Array
(
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[patent_doc_number] => 20030104668
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[patent_issue_date] => 2003-06-05
[patent_title] => 'Capacitor structure of semiconductor device and method for forming the same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/279682 | Capacitor structure of semiconductor device and method for forming the same | Oct 23, 2002 | Issued |
Array
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[patent_issue_date] => 2003-10-30
[patent_title] => 'Process of forming copper structures'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/279057 | Process of forming copper structures | Oct 23, 2002 | Issued |
Array
(
[id] => 1205466
[patent_doc_number] => 06716682
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[patent_issue_date] => 2004-04-06
[patent_title] => 'SOI CMOS device with reduced DIBL'
[patent_app_type] => B1
[patent_app_number] => 10/268578
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[patent_app_date] => 2002-10-10
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/268578 | SOI CMOS device with reduced DIBL | Oct 9, 2002 | Issued |
Array
(
[id] => 7310109
[patent_doc_number] => 20040032003
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[patent_issue_date] => 2004-02-19
[patent_title] => 'Semiconductor device fabricated on surface of silicon having <110>direction of crystal plane and its production method'
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[patent_app_number] => 10/416969
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Array
(
[id] => 6750545
[patent_doc_number] => 20030045065
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[patent_issue_date] => 2003-03-06
[patent_title] => 'Method of producing a semiconductor integrated circuit device and the semiconductor integrated circuit device'
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[patent_app_date] => 2002-09-27
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/256027 | Method of producing a semiconductor integrated circuit device and the semiconductor integrated circuit device | Sep 26, 2002 | Abandoned |
Array
(
[id] => 7634835
[patent_doc_number] => 06656783
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[patent_issue_date] => 2003-12-02
[patent_title] => 'Semiconductor device having shallow trench isolation structure and manufacturing method thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/255526 | Semiconductor device having shallow trench isolation structure and manufacturing method thereof | Sep 24, 2002 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/251975 | Semiconductor device and method for fabricating the same | Sep 22, 2002 | Issued |
Array
(
[id] => 6807316
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Array
(
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Array
(
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Array
(
[id] => 7135200
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[patent_title] => 'METHOD FOR CREATING A DAMASCENE INTERCONNECT USING A TWO-STEP ELECTROPLATING PROCESS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/232684 | Method for creating a damascene interconnect using a two-step electroplating process | Sep 2, 2002 | Issued |
Array
(
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[patent_title] => 'Semiconductor devices with conductive lines that are laterally offset relative to corresponding contacts'
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/225228 | Method of forming a barrier film and method of forming wiring structure and electrodes of semiconductor device having a barrier film | Aug 21, 2002 | Issued |