Barbara J Bullock
Examiner (ID: 9881)
Most Active Art Unit | 2901 |
Art Unit(s) | 2900, 2912, 2901, 2902 |
Total Applications | 4468 |
Issued Applications | 4372 |
Pending Applications | 0 |
Abandoned Applications | 96 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 7395021
[patent_doc_number] => 20040038478
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-02-26
[patent_title] => 'DUAL-DAMASCENE BIT LINE STRUCTURES FOR MICROELECTRONIC DEVICES AND METHODS OF FABRICATING MICROELECTRONIC DEVICES'
[patent_app_type] => new
[patent_app_number] => 10/225584
[patent_app_country] => US
[patent_app_date] => 2002-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 6435
[patent_no_of_claims] => 52
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0038/20040038478.pdf
[firstpage_image] =>[orig_patent_app_number] => 10225584
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/225584 | Dual-damascene bit line structures for microelectronic devices and methods of fabricating microelectronic devices | Aug 20, 2002 | Issued |
Array
(
[id] => 1299728
[patent_doc_number] => 06624054
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-09-23
[patent_title] => 'Multi-layer structure for reducing capacitance and manufacturing method thereof'
[patent_app_type] => B1
[patent_app_number] => 10/224933
[patent_app_country] => US
[patent_app_date] => 2002-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 1687
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/624/06624054.pdf
[firstpage_image] =>[orig_patent_app_number] => 10224933
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/224933 | Multi-layer structure for reducing capacitance and manufacturing method thereof | Aug 20, 2002 | Issued |
Array
(
[id] => 6690910
[patent_doc_number] => 20030038342
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-02-27
[patent_title] => 'Wafer level underfill and interconnect process'
[patent_app_type] => new
[patent_app_number] => 10/225399
[patent_app_country] => US
[patent_app_date] => 2002-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2310
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0038/20030038342.pdf
[firstpage_image] =>[orig_patent_app_number] => 10225399
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/225399 | Wafer level underfill and interconnect process | Aug 19, 2002 | Issued |
Array
(
[id] => 1336378
[patent_doc_number] => 06593221
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-07-15
[patent_title] => 'Selective passivation of exposed silicon'
[patent_app_type] => B1
[patent_app_number] => 10/218268
[patent_app_country] => US
[patent_app_date] => 2002-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 4454
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/593/06593221.pdf
[firstpage_image] =>[orig_patent_app_number] => 10218268
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/218268 | Selective passivation of exposed silicon | Aug 12, 2002 | Issued |
Array
(
[id] => 1303079
[patent_doc_number] => 06620726
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-09-16
[patent_title] => 'Method of forming metal lines having improved uniformity on a substrate'
[patent_app_type] => B1
[patent_app_number] => 10/208764
[patent_app_country] => US
[patent_app_date] => 2002-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 6285
[patent_no_of_claims] => 57
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/620/06620726.pdf
[firstpage_image] =>[orig_patent_app_number] => 10208764
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/208764 | Method of forming metal lines having improved uniformity on a substrate | Jul 29, 2002 | Issued |
Array
(
[id] => 1096002
[patent_doc_number] => 06821859
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-11-23
[patent_title] => 'Method and system for controlling an electrical property of a field effect transistor'
[patent_app_type] => B2
[patent_app_number] => 10/208564
[patent_app_country] => US
[patent_app_date] => 2002-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 7056
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/821/06821859.pdf
[firstpage_image] =>[orig_patent_app_number] => 10208564
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/208564 | Method and system for controlling an electrical property of a field effect transistor | Jul 29, 2002 | Issued |
Array
(
[id] => 7398959
[patent_doc_number] => 20040018712
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-29
[patent_title] => 'METHOD OF FORMING A THROUGH-SUBSTRATE INTERCONNECT'
[patent_app_type] => new
[patent_app_number] => 10/208363
[patent_app_country] => US
[patent_app_date] => 2002-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7686
[patent_no_of_claims] => 67
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0018/20040018712.pdf
[firstpage_image] =>[orig_patent_app_number] => 10208363
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/208363 | Method of forming a through-substrate interconnect | Jul 28, 2002 | Issued |
Array
(
[id] => 1050012
[patent_doc_number] => 06861289
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-03-01
[patent_title] => 'Moisture-sensitive device protection system'
[patent_app_type] => utility
[patent_app_number] => 10/202988
[patent_app_country] => US
[patent_app_date] => 2002-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 2720
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/861/06861289.pdf
[firstpage_image] =>[orig_patent_app_number] => 10202988
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/202988 | Moisture-sensitive device protection system | Jul 24, 2002 | Issued |
Array
(
[id] => 7036853
[patent_doc_number] => 20050156287
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-21
[patent_title] => 'Organic polymer film, method for producing the same and semiconductor device using the same'
[patent_app_type] => utility
[patent_app_number] => 10/484893
[patent_app_country] => US
[patent_app_date] => 2002-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5364
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0156/20050156287.pdf
[firstpage_image] =>[orig_patent_app_number] => 10484893
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/484893 | Organic polymer film, method for producing the same and semiconductor device using the same | Jul 21, 2002 | Abandoned |
Array
(
[id] => 1245741
[patent_doc_number] => 06677230
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-01-13
[patent_title] => 'Method of manufacturing semiconductor device'
[patent_app_type] => B2
[patent_app_number] => 10/197411
[patent_app_country] => US
[patent_app_date] => 2002-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 56
[patent_no_of_words] => 17421
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/677/06677230.pdf
[firstpage_image] =>[orig_patent_app_number] => 10197411
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/197411 | Method of manufacturing semiconductor device | Jul 17, 2002 | Issued |
Array
(
[id] => 975984
[patent_doc_number] => 06933601
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-08-23
[patent_title] => 'Semiconductor connection substrate'
[patent_app_type] => utility
[patent_app_number] => 10/483383
[patent_app_country] => US
[patent_app_date] => 2002-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 28218
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/933/06933601.pdf
[firstpage_image] =>[orig_patent_app_number] => 10483383
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/483383 | Semiconductor connection substrate | Jul 11, 2002 | Issued |
Array
(
[id] => 7445977
[patent_doc_number] => 20040009633
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-15
[patent_title] => 'METHOD OF USING HIGH-K DIELECTRIC MATERIALS TO REDUCE SOFT ERRORS IN SRAM MEMORY CELLS, AND A DEVICE COMPRISING SAME'
[patent_app_type] => new
[patent_app_number] => 10/191833
[patent_app_country] => US
[patent_app_date] => 2002-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3785
[patent_no_of_claims] => 52
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0009/20040009633.pdf
[firstpage_image] =>[orig_patent_app_number] => 10191833
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/191833 | Method of using high-k dielectric materials to reduce soft errors in SRAM memory cells, and a device comprising same | Jul 8, 2002 | Issued |
Array
(
[id] => 1270309
[patent_doc_number] => 06653223
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-11-25
[patent_title] => 'Dual damascene method employing void forming via filling dielectric layer'
[patent_app_type] => B1
[patent_app_number] => 10/192033
[patent_app_country] => US
[patent_app_date] => 2002-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 4
[patent_no_of_words] => 3251
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/653/06653223.pdf
[firstpage_image] =>[orig_patent_app_number] => 10192033
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/192033 | Dual damascene method employing void forming via filling dielectric layer | Jul 8, 2002 | Issued |
Array
(
[id] => 1336476
[patent_doc_number] => 06593232
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-07-15
[patent_title] => 'Plasma etch method with enhanced endpoint detection'
[patent_app_type] => B1
[patent_app_number] => 10/190253
[patent_app_country] => US
[patent_app_date] => 2002-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 3441
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/593/06593232.pdf
[firstpage_image] =>[orig_patent_app_number] => 10190253
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/190253 | Plasma etch method with enhanced endpoint detection | Jul 4, 2002 | Issued |
Array
(
[id] => 6107220
[patent_doc_number] => 20020171150
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-21
[patent_title] => 'Method for producing a micromechanical structure and a micromechanical structure'
[patent_app_type] => new
[patent_app_number] => 10/188684
[patent_app_country] => US
[patent_app_date] => 2002-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1777
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0171/20020171150.pdf
[firstpage_image] =>[orig_patent_app_number] => 10188684
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/188684 | Method for producing a micromechanical structure and a micromechanical structure | Jul 2, 2002 | Issued |
Array
(
[id] => 6735640
[patent_doc_number] => 20030013275
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-16
[patent_title] => 'Isotopically pure silicon-on-insulator wafers and method of making same'
[patent_app_type] => new
[patent_app_number] => 10/189732
[patent_app_country] => US
[patent_app_date] => 2002-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2232
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 16
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0013/20030013275.pdf
[firstpage_image] =>[orig_patent_app_number] => 10189732
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/189732 | Isotopically pure silicon-on-insulator wafers and method of making same | Jul 2, 2002 | Issued |
Array
(
[id] => 6688508
[patent_doc_number] => 20030032233
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-02-13
[patent_title] => 'Method for manufacturing semiconductor integrated circuit device'
[patent_app_type] => new
[patent_app_number] => 10/187003
[patent_app_country] => US
[patent_app_date] => 2002-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 10423
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0032/20030032233.pdf
[firstpage_image] =>[orig_patent_app_number] => 10187003
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/187003 | Method for manufacturing semiconductor integrated circuit device | Jul 1, 2002 | Issued |
Array
(
[id] => 1281148
[patent_doc_number] => 06642139
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-11-04
[patent_title] => 'Method for forming interconnection structure in an integration circuit'
[patent_app_type] => B1
[patent_app_number] => 10/187134
[patent_app_country] => US
[patent_app_date] => 2002-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 16
[patent_no_of_words] => 1865
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/642/06642139.pdf
[firstpage_image] =>[orig_patent_app_number] => 10187134
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/187134 | Method for forming interconnection structure in an integration circuit | Jun 27, 2002 | Issued |
Array
(
[id] => 6107156
[patent_doc_number] => 20020171109
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-21
[patent_title] => 'Semiconductor device with SOI structure and method of manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 10/178429
[patent_app_country] => US
[patent_app_date] => 2002-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 49
[patent_figures_cnt] => 49
[patent_no_of_words] => 9361
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0171/20020171109.pdf
[firstpage_image] =>[orig_patent_app_number] => 10178429
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/178429 | Semiconductor device with SOI structure and method of manufacturing the same | Jun 23, 2002 | Issued |
Array
(
[id] => 6825364
[patent_doc_number] => 20030235986
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-12-25
[patent_title] => 'Silicon oxide etching compositions with reduced water content'
[patent_app_type] => new
[patent_app_number] => 10/176278
[patent_app_country] => US
[patent_app_date] => 2002-06-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3220
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 48
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0235/20030235986.pdf
[firstpage_image] =>[orig_patent_app_number] => 10176278
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/176278 | Silicon oxide etching compositions with reduced water content | Jun 19, 2002 | Abandoned |