Search

Barbara J Bullock

Examiner (ID: 9881)

Most Active Art Unit
2901
Art Unit(s)
2900, 2912, 2901, 2902
Total Applications
4468
Issued Applications
4372
Pending Applications
0
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1312353 [patent_doc_number] => 06610599 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-26 [patent_title] => 'Removal of metal veils from via holes' [patent_app_type] => B1 [patent_app_number] => 10/175459 [patent_app_country] => US [patent_app_date] => 2002-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3911 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/610/06610599.pdf [firstpage_image] =>[orig_patent_app_number] => 10175459 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/175459
Removal of metal veils from via holes Jun 18, 2002 Issued
Array ( [id] => 6444814 [patent_doc_number] => 20020149085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-17 [patent_title] => 'Method of manufacturing air gap in multilevel interconnection' [patent_app_type] => new [patent_app_number] => 10/167863 [patent_app_country] => US [patent_app_date] => 2002-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2802 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20020149085.pdf [firstpage_image] =>[orig_patent_app_number] => 10167863 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/167863
Method of manufacturing air gap in multilevel interconnection Jun 10, 2002 Abandoned
Array ( [id] => 6676951 [patent_doc_number] => 20030227091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-11 [patent_title] => 'Plating metal caps on conductive interconnect for wirebonding' [patent_app_type] => new [patent_app_number] => 10/162673 [patent_app_country] => US [patent_app_date] => 2002-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2643 [patent_no_of_claims] => 129 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20030227091.pdf [firstpage_image] =>[orig_patent_app_number] => 10162673 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/162673
Plating metal caps on conductive interconnect for wirebonding Jun 5, 2002 Abandoned
Array ( [id] => 1314559 [patent_doc_number] => 06614116 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-02 [patent_title] => 'Buried digit line stack and process for making same' [patent_app_type] => B1 [patent_app_number] => 10/163289 [patent_app_country] => US [patent_app_date] => 2002-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 7917 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/614/06614116.pdf [firstpage_image] =>[orig_patent_app_number] => 10163289 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/163289
Buried digit line stack and process for making same Jun 3, 2002 Issued
Array ( [id] => 6408501 [patent_doc_number] => 20020182783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Semiconductor film, semiconductor device and method for manufacturing same' [patent_app_type] => new [patent_app_number] => 10/157843 [patent_app_country] => US [patent_app_date] => 2002-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9225 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20020182783.pdf [firstpage_image] =>[orig_patent_app_number] => 10157843 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/157843
Semiconductor film, semiconductor device and method for manufacturing same May 30, 2002 Issued
Array ( [id] => 1339918 [patent_doc_number] => 06589852 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'Method of replicating alignment marks for semiconductor wafer photolithography' [patent_app_type] => B1 [patent_app_number] => 10/154463 [patent_app_country] => US [patent_app_date] => 2002-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 3557 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/589/06589852.pdf [firstpage_image] =>[orig_patent_app_number] => 10154463 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/154463
Method of replicating alignment marks for semiconductor wafer photolithography May 22, 2002 Issued
Array ( [id] => 6636175 [patent_doc_number] => 20030211695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-13 [patent_title] => 'METHODS OF FABRICATING HIGH DENSITY MASK ROM CELLS' [patent_app_type] => new [patent_app_number] => 10/144874 [patent_app_country] => US [patent_app_date] => 2002-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6329 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20030211695.pdf [firstpage_image] =>[orig_patent_app_number] => 10144874 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/144874
Methods of fabricating high density mask ROM cells May 12, 2002 Issued
Array ( [id] => 6671922 [patent_doc_number] => 20030057525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Flexible integrated monolithic circuit' [patent_app_type] => new [patent_app_number] => 10/140663 [patent_app_country] => US [patent_app_date] => 2002-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4209 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20030057525.pdf [firstpage_image] =>[orig_patent_app_number] => 10140663 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/140663
Flexible integrated monolithic circuit May 7, 2002 Issued
Array ( [id] => 1367592 [patent_doc_number] => 06566244 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Process for improving mechanical strength of layers of low k dielectric material' [patent_app_type] => B1 [patent_app_number] => 10/138609 [patent_app_country] => US [patent_app_date] => 2002-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3418 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/566/06566244.pdf [firstpage_image] =>[orig_patent_app_number] => 10138609 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/138609
Process for improving mechanical strength of layers of low k dielectric material May 2, 2002 Issued
Array ( [id] => 6366391 [patent_doc_number] => 20020117752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-29 [patent_title] => 'Integrated circuit contact' [patent_app_type] => new [patent_app_number] => 10/136126 [patent_app_country] => US [patent_app_date] => 2002-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2391 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20020117752.pdf [firstpage_image] =>[orig_patent_app_number] => 10136126 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/136126
Integrated circuit contact Apr 30, 2002 Issued
Array ( [id] => 1178465 [patent_doc_number] => 06747312 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-08 [patent_title] => 'Rad hard MOSFET with graded body diode junction and reduced on resistance' [patent_app_type] => B2 [patent_app_number] => 10/138164 [patent_app_country] => US [patent_app_date] => 2002-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2531 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/747/06747312.pdf [firstpage_image] =>[orig_patent_app_number] => 10138164 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/138164
Rad hard MOSFET with graded body diode junction and reduced on resistance Apr 30, 2002 Issued
10/133782 Copper silicide passivation for improved reliability Apr 25, 2002 Abandoned
Array ( [id] => 1336444 [patent_doc_number] => 06593228 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-15 [patent_title] => 'Method of fabricating a patterned metal-containing layer on a semiconductor wafer' [patent_app_type] => B2 [patent_app_number] => 10/122936 [patent_app_country] => US [patent_app_date] => 2002-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3484 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/593/06593228.pdf [firstpage_image] =>[orig_patent_app_number] => 10122936 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/122936
Method of fabricating a patterned metal-containing layer on a semiconductor wafer Apr 11, 2002 Issued
Array ( [id] => 7629824 [patent_doc_number] => 06818532 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-16 [patent_title] => 'Method of etching substrates' [patent_app_type] => B2 [patent_app_number] => 10/118318 [patent_app_country] => US [patent_app_date] => 2002-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 5576 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 8 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/818/06818532.pdf [firstpage_image] =>[orig_patent_app_number] => 10118318 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/118318
Method of etching substrates Apr 8, 2002 Issued
Array ( [id] => 5787482 [patent_doc_number] => 20020160607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-31 [patent_title] => 'Electrode pad in semiconductor device and method of producing the same' [patent_app_type] => new [patent_app_number] => 10/117688 [patent_app_country] => US [patent_app_date] => 2002-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1886 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20020160607.pdf [firstpage_image] =>[orig_patent_app_number] => 10117688 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/117688
Electrode pad in semiconductor device and method of producing the same Apr 4, 2002 Issued
Array ( [id] => 6742986 [patent_doc_number] => 20030020169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-30 [patent_title] => 'Copper technology for ULSI metallization' [patent_app_type] => new [patent_app_number] => 10/109713 [patent_app_country] => US [patent_app_date] => 2002-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4026 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20030020169.pdf [firstpage_image] =>[orig_patent_app_number] => 10109713 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/109713
Copper technology for ULSI metallization Mar 31, 2002 Abandoned
Array ( [id] => 1284632 [patent_doc_number] => 06642606 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-04 [patent_title] => 'Method for producing siliconized polysilicon contacts in integrated semiconductor structures' [patent_app_type] => B1 [patent_app_number] => 10/030358 [patent_app_country] => US [patent_app_date] => 2002-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3576 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/642/06642606.pdf [firstpage_image] =>[orig_patent_app_number] => 10030358 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/030358
Method for producing siliconized polysilicon contacts in integrated semiconductor structures Mar 25, 2002 Issued
10/105428 Method for contact profile improvement Mar 25, 2002 Abandoned
Array ( [id] => 6016417 [patent_doc_number] => 20020102806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-01 [patent_title] => 'Method of producing a thin film resistor in an integrated circuit' [patent_app_type] => new [patent_app_number] => 10/102290 [patent_app_country] => US [patent_app_date] => 2002-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2148 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20020102806.pdf [firstpage_image] =>[orig_patent_app_number] => 10102290 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/102290
Method of producing a thin film resistor in an integrated circuit Mar 19, 2002 Issued
Array ( [id] => 6795602 [patent_doc_number] => 20030174475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-18 [patent_title] => 'Chip with passive electrical contacts' [patent_app_type] => new [patent_app_number] => 10/099593 [patent_app_country] => US [patent_app_date] => 2002-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 19887 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20030174475.pdf [firstpage_image] =>[orig_patent_app_number] => 10099593 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/099593
Chip with passive electrical contacts Mar 15, 2002 Issued
Menu