Search

Barbara J Bullock

Examiner (ID: 9881)

Most Active Art Unit
2901
Art Unit(s)
2900, 2912, 2901, 2902
Total Applications
4468
Issued Applications
4372
Pending Applications
0
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1500409 [patent_doc_number] => 06486055 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Method for forming copper interconnections in semiconductor component using electroless plating system' [patent_app_type] => B1 [patent_app_number] => 10/097308 [patent_app_country] => US [patent_app_date] => 2002-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 31 [patent_no_of_words] => 5111 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/486/06486055.pdf [firstpage_image] =>[orig_patent_app_number] => 10097308 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/097308
Method for forming copper interconnections in semiconductor component using electroless plating system Mar 14, 2002 Issued
Array ( [id] => 1264359 [patent_doc_number] => 06660576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-09 [patent_title] => 'Substrate and method for producing variable quality substrate material' [patent_app_type] => B2 [patent_app_number] => 10/096293 [patent_app_country] => US [patent_app_date] => 2002-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4367 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/660/06660576.pdf [firstpage_image] =>[orig_patent_app_number] => 10096293 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/096293
Substrate and method for producing variable quality substrate material Mar 10, 2002 Issued
Array ( [id] => 6711184 [patent_doc_number] => 20030170933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-11 [patent_title] => 'SYSTEM FOR PROVIDING AN OPEN-CAVITY LOW PROFILE ENCAPSULATED SEMICONDUCTOR PACKAGE' [patent_app_type] => new [patent_app_number] => 10/094954 [patent_app_country] => US [patent_app_date] => 2002-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5234 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20030170933.pdf [firstpage_image] =>[orig_patent_app_number] => 10094954 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/094954
System for providing an open-cavity low profile encapsulated semiconductor package Mar 8, 2002 Issued
Array ( [id] => 1364478 [patent_doc_number] => 06573570 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-03 [patent_title] => 'Semiconductor device having contact electrode to semiconductor substrate' [patent_app_type] => B2 [patent_app_number] => 10/093788 [patent_app_country] => US [patent_app_date] => 2002-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 44 [patent_no_of_words] => 6949 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/573/06573570.pdf [firstpage_image] =>[orig_patent_app_number] => 10093788 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/093788
Semiconductor device having contact electrode to semiconductor substrate Mar 5, 2002 Issued
Array ( [id] => 1336411 [patent_doc_number] => 06593224 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'Method of manufacturing a multilayer interconnect substrate' [patent_app_type] => B1 [patent_app_number] => 10/091683 [patent_app_country] => US [patent_app_date] => 2002-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 53 [patent_no_of_words] => 9312 [patent_no_of_claims] => 100 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/593/06593224.pdf [firstpage_image] =>[orig_patent_app_number] => 10091683 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/091683
Method of manufacturing a multilayer interconnect substrate Mar 4, 2002 Issued
Array ( [id] => 1467050 [patent_doc_number] => 06458692 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Method of forming contact plug of semiconductor device' [patent_app_type] => B1 [patent_app_number] => 10/080939 [patent_app_country] => US [patent_app_date] => 2002-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4186 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/458/06458692.pdf [firstpage_image] =>[orig_patent_app_number] => 10080939 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/080939
Method of forming contact plug of semiconductor device Feb 21, 2002 Issued
Array ( [id] => 1326952 [patent_doc_number] => 06599785 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-29 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/078414 [patent_app_country] => US [patent_app_date] => 2002-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 53 [patent_no_of_words] => 20164 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/599/06599785.pdf [firstpage_image] =>[orig_patent_app_number] => 10078414 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/078414
Method of manufacturing a semiconductor device Feb 20, 2002 Issued
Array ( [id] => 1272958 [patent_doc_number] => 06653734 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-25 [patent_title] => 'Convertible hot edge ring to improve low-K dielectric etch' [patent_app_type] => B2 [patent_app_number] => 10/066118 [patent_app_country] => US [patent_app_date] => 2002-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 7323 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/653/06653734.pdf [firstpage_image] =>[orig_patent_app_number] => 10066118 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/066118
Convertible hot edge ring to improve low-K dielectric etch Jan 29, 2002 Issued
Array ( [id] => 6015527 [patent_doc_number] => 20020102496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-01 [patent_title] => 'Thin film circuit substrate and manufacturing method therefor' [patent_app_type] => new [patent_app_number] => 10/059629 [patent_app_country] => US [patent_app_date] => 2002-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7383 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20020102496.pdf [firstpage_image] =>[orig_patent_app_number] => 10059629 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/059629
Thin film circuit substrate and manufacturing method therefor Jan 28, 2002 Issued
Array ( [id] => 1412557 [patent_doc_number] => 06524942 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-25 [patent_title] => 'Bond pad structure and its method of fabricating' [patent_app_type] => B2 [patent_app_number] => 10/056004 [patent_app_country] => US [patent_app_date] => 2002-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3435 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/524/06524942.pdf [firstpage_image] =>[orig_patent_app_number] => 10056004 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/056004
Bond pad structure and its method of fabricating Jan 27, 2002 Issued
Array ( [id] => 6659729 [patent_doc_number] => 20030134495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-17 [patent_title] => 'Integration scheme for advanced BEOL metallization including low-k cap layer and method thereof' [patent_app_type] => new [patent_app_number] => 10/047968 [patent_app_country] => US [patent_app_date] => 2002-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5722 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20030134495.pdf [firstpage_image] =>[orig_patent_app_number] => 10047968 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/047968
Integration scheme for advanced BEOL metallization including low-k cap layer and method thereof Jan 14, 2002 Abandoned
Array ( [id] => 1376225 [patent_doc_number] => 06559043 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Method for electrical interconnection employing salicide bridge' [patent_app_type] => B1 [patent_app_number] => 10/043482 [patent_app_country] => US [patent_app_date] => 2002-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 5215 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/559/06559043.pdf [firstpage_image] =>[orig_patent_app_number] => 10043482 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/043482
Method for electrical interconnection employing salicide bridge Jan 10, 2002 Issued
Array ( [id] => 6530677 [patent_doc_number] => 20020192932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-19 [patent_title] => 'Salicide integration process' [patent_app_type] => new [patent_app_number] => 10/042419 [patent_app_country] => US [patent_app_date] => 2002-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2770 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0192/20020192932.pdf [firstpage_image] =>[orig_patent_app_number] => 10042419 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/042419
Salicide integration process Jan 8, 2002 Abandoned
Array ( [id] => 6306590 [patent_doc_number] => 20020094610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-18 [patent_title] => 'Method of producing a semiconductor integrated circuit device and the semiconductor integrated circuit device' [patent_app_type] => new [patent_app_number] => 10/036449 [patent_app_country] => US [patent_app_date] => 2002-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 51 [patent_no_of_words] => 15683 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20020094610.pdf [firstpage_image] =>[orig_patent_app_number] => 10036449 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/036449
Method of producing a semiconductor integrated circuit device and the semiconductor integrated circuit device Jan 6, 2002 Issued
Array ( [id] => 1399381 [patent_doc_number] => 06537909 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Method of preventing silicide spiking' [patent_app_type] => B1 [patent_app_number] => 09/683468 [patent_app_country] => US [patent_app_date] => 2002-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1817 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/537/06537909.pdf [firstpage_image] =>[orig_patent_app_number] => 09683468 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/683468
Method of preventing silicide spiking Jan 2, 2002 Issued
Array ( [id] => 6750571 [patent_doc_number] => 20030045091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'Method of forming a contact for a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/034497 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2225 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20030045091.pdf [firstpage_image] =>[orig_patent_app_number] => 10034497 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/034497
Method of forming a contact for a semiconductor device Dec 27, 2001 Abandoned
Array ( [id] => 1379373 [patent_doc_number] => 06555463 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-29 [patent_title] => 'Methods of fabricating buried digit lines' [patent_app_type] => B2 [patent_app_number] => 10/032730 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 4916 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/555/06555463.pdf [firstpage_image] =>[orig_patent_app_number] => 10032730 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/032730
Methods of fabricating buried digit lines Dec 27, 2001 Issued
Array ( [id] => 5859329 [patent_doc_number] => 20020123216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-05 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => new [patent_app_number] => 10/026708 [patent_app_country] => US [patent_app_date] => 2001-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 17566 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20020123216.pdf [firstpage_image] =>[orig_patent_app_number] => 10026708 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/026708
Method of manufacturing semiconductor device Dec 26, 2001 Issued
Array ( [id] => 1270314 [patent_doc_number] => 06653224 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-25 [patent_title] => 'Methods for fabricating interconnect structures having Low K dielectric properties' [patent_app_type] => B1 [patent_app_number] => 10/032480 [patent_app_country] => US [patent_app_date] => 2001-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6219 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/653/06653224.pdf [firstpage_image] =>[orig_patent_app_number] => 10032480 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/032480
Methods for fabricating interconnect structures having Low K dielectric properties Dec 26, 2001 Issued
Array ( [id] => 1402298 [patent_doc_number] => 06534402 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Method of fabricating self-aligned silicide' [patent_app_type] => B1 [patent_app_number] => 10/025430 [patent_app_country] => US [patent_app_date] => 2001-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2360 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/534/06534402.pdf [firstpage_image] =>[orig_patent_app_number] => 10025430 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/025430
Method of fabricating self-aligned silicide Dec 18, 2001 Issued
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