Search

Barbara J Bullock

Examiner (ID: 9881)

Most Active Art Unit
2901
Art Unit(s)
2900, 2912, 2901, 2902
Total Applications
4468
Issued Applications
4372
Pending Applications
0
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6435269 [patent_doc_number] => 20020127851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'Method of producing semiconductor device' [patent_app_type] => new [patent_app_number] => 10/020118 [patent_app_country] => US [patent_app_date] => 2001-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2851 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20020127851.pdf [firstpage_image] =>[orig_patent_app_number] => 10020118 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/020118
Method of producing semiconductor device Dec 17, 2001 Abandoned
Array ( [id] => 6306651 [patent_doc_number] => 20020094624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-18 [patent_title] => 'Method for forming cell capacitor for high-integrated DRAMs' [patent_app_type] => new [patent_app_number] => 10/020649 [patent_app_country] => US [patent_app_date] => 2001-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1550 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20020094624.pdf [firstpage_image] =>[orig_patent_app_number] => 10020649 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/020649
Method for forming cell capacitor for high-integrated DRAMs Dec 11, 2001 Issued
Array ( [id] => 1514535 [patent_doc_number] => 06420254 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Recessed bond pad' [patent_app_type] => B1 [patent_app_number] => 09/996538 [patent_app_country] => US [patent_app_date] => 2001-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9861 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/420/06420254.pdf [firstpage_image] =>[orig_patent_app_number] => 09996538 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/996538
Recessed bond pad Nov 27, 2001 Issued
Array ( [id] => 1299771 [patent_doc_number] => 06624062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-23 [patent_title] => 'Wiring structure in semiconductor device and method for forming the same' [patent_app_type] => B2 [patent_app_number] => 09/993517 [patent_app_country] => US [patent_app_date] => 2001-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 9432 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/624/06624062.pdf [firstpage_image] =>[orig_patent_app_number] => 09993517 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/993517
Wiring structure in semiconductor device and method for forming the same Nov 26, 2001 Issued
Array ( [id] => 1468504 [patent_doc_number] => 06459117 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Integrated circuit device formed with high Q MIM capacitor' [patent_app_type] => B1 [patent_app_number] => 09/994398 [patent_app_country] => US [patent_app_date] => 2001-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2794 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/459/06459117.pdf [firstpage_image] =>[orig_patent_app_number] => 09994398 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/994398
Integrated circuit device formed with high Q MIM capacitor Nov 25, 2001 Issued
Array ( [id] => 6494756 [patent_doc_number] => 20020190380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-19 [patent_title] => 'SEMICONDUCTOR DEVICE INCLUDING A PAD AND A METHOD OF MANUFACTURING THE SAME' [patent_app_type] => new [patent_app_number] => 09/988268 [patent_app_country] => US [patent_app_date] => 2001-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5970 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20020190380.pdf [firstpage_image] =>[orig_patent_app_number] => 09988268 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/988268
Semiconductor device including a pad and a method of manufacturing the same Nov 18, 2001 Issued
Array ( [id] => 6858988 [patent_doc_number] => 20030089996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-15 [patent_title] => 'Electromigration-reliability improvement of dual damascene interconnects' [patent_app_type] => new [patent_app_number] => 10/010679 [patent_app_country] => US [patent_app_date] => 2001-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3782 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20030089996.pdf [firstpage_image] =>[orig_patent_app_number] => 10010679 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/010679
Electromigration-reliability improvement of dual damascene interconnects Nov 12, 2001 Issued
Array ( [id] => 6359090 [patent_doc_number] => 20020058371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-16 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => new [patent_app_number] => 09/987029 [patent_app_country] => US [patent_app_date] => 2001-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5233 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20020058371.pdf [firstpage_image] =>[orig_patent_app_number] => 09987029 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/987029
Method of manufacturing semiconductor device Nov 12, 2001 Issued
Array ( [id] => 996556 [patent_doc_number] => 06913996 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-05 [patent_title] => 'Method of forming metal wiring and semiconductor manufacturing apparatus for forming metal wiring' [patent_app_type] => utility [patent_app_number] => 10/181273 [patent_app_country] => US [patent_app_date] => 2001-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6128 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/913/06913996.pdf [firstpage_image] =>[orig_patent_app_number] => 10181273 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/181273
Method of forming metal wiring and semiconductor manufacturing apparatus for forming metal wiring Nov 12, 2001 Issued
Array ( [id] => 1559883 [patent_doc_number] => 06436821 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Method for producing a micromechanical structure and a micromechanical structure' [patent_app_type] => B1 [patent_app_number] => 09/992939 [patent_app_country] => US [patent_app_date] => 2001-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 1750 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/436/06436821.pdf [firstpage_image] =>[orig_patent_app_number] => 09992939 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/992939
Method for producing a micromechanical structure and a micromechanical structure Nov 4, 2001 Issued
Array ( [id] => 1500401 [patent_doc_number] => 06486053 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-26 [patent_title] => 'Semiconductor device and fabricating method therefor' [patent_app_type] => B2 [patent_app_number] => 10/000416 [patent_app_country] => US [patent_app_date] => 2001-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3425 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/486/06486053.pdf [firstpage_image] =>[orig_patent_app_number] => 10000416 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/000416
Semiconductor device and fabricating method therefor Nov 1, 2001 Issued
Array ( [id] => 6091977 [patent_doc_number] => 20020050605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-02 [patent_title] => 'Method to reduce contact distortion in devices having silicide contacts' [patent_app_type] => new [patent_app_number] => 09/984868 [patent_app_country] => US [patent_app_date] => 2001-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3965 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20020050605.pdf [firstpage_image] =>[orig_patent_app_number] => 09984868 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/984868
Method to reduce contact distortion in devices having silicide contacts Oct 30, 2001 Abandoned
Array ( [id] => 1600441 [patent_doc_number] => 06475891 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-05 [patent_title] => 'Method of forming a pattern for a semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/984949 [patent_app_country] => US [patent_app_date] => 2001-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3428 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/475/06475891.pdf [firstpage_image] =>[orig_patent_app_number] => 09984949 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/984949
Method of forming a pattern for a semiconductor device Oct 30, 2001 Issued
Array ( [id] => 1196697 [patent_doc_number] => 06727168 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-27 [patent_title] => 'Method of forming local interconnects' [patent_app_type] => B2 [patent_app_number] => 10/001758 [patent_app_country] => US [patent_app_date] => 2001-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2912 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/727/06727168.pdf [firstpage_image] =>[orig_patent_app_number] => 10001758 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/001758
Method of forming local interconnects Oct 23, 2001 Issued
Array ( [id] => 6033040 [patent_doc_number] => 20020019127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-14 [patent_title] => 'Interconnect structure and method of making' [patent_app_type] => new [patent_app_number] => 09/982191 [patent_app_country] => US [patent_app_date] => 2001-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6697 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20020019127.pdf [firstpage_image] =>[orig_patent_app_number] => 09982191 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/982191
Interconnect structure and method of making Oct 17, 2001 Abandoned
Array ( [id] => 1327288 [patent_doc_number] => 06599828 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-29 [patent_title] => 'Copper reflow process' [patent_app_type] => B1 [patent_app_number] => 09/982575 [patent_app_country] => US [patent_app_date] => 2001-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 14 [patent_no_of_words] => 5423 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/599/06599828.pdf [firstpage_image] =>[orig_patent_app_number] => 09982575 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/982575
Copper reflow process Oct 16, 2001 Issued
Array ( [id] => 6502083 [patent_doc_number] => 20020025605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-28 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/978068 [patent_app_country] => US [patent_app_date] => 2001-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 15283 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20020025605.pdf [firstpage_image] =>[orig_patent_app_number] => 09978068 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/978068
Semiconductor device and method for manufacturing the same Oct 16, 2001 Abandoned
Array ( [id] => 1600482 [patent_doc_number] => 06475899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-05 [patent_title] => 'Low capacitance wiring layout and method for making same' [patent_app_type] => B2 [patent_app_number] => 09/978071 [patent_app_country] => US [patent_app_date] => 2001-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 31 [patent_no_of_words] => 4950 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/475/06475899.pdf [firstpage_image] =>[orig_patent_app_number] => 09978071 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/978071
Low capacitance wiring layout and method for making same Oct 16, 2001 Issued
Array ( [id] => 5874132 [patent_doc_number] => 20020048947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'Semiconductor integrated circuit device and the process of the same' [patent_app_type] => new [patent_app_number] => 09/974814 [patent_app_country] => US [patent_app_date] => 2001-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5916 [patent_no_of_claims] => 70 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20020048947.pdf [firstpage_image] =>[orig_patent_app_number] => 09974814 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/974814
Semiconductor integrated circuit device and the process of the same Oct 11, 2001 Issued
Array ( [id] => 1517338 [patent_doc_number] => 06500748 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-31 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => B2 [patent_app_number] => 09/974045 [patent_app_country] => US [patent_app_date] => 2001-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 45 [patent_no_of_words] => 8552 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/500/06500748.pdf [firstpage_image] =>[orig_patent_app_number] => 09974045 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/974045
Semiconductor device and method of manufacturing the same Oct 10, 2001 Issued
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