Search

Barbara J Bullock

Examiner (ID: 9881)

Most Active Art Unit
2901
Art Unit(s)
2900, 2912, 2901, 2902
Total Applications
4468
Issued Applications
4372
Pending Applications
0
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1536566 [patent_doc_number] => 06489683 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Variable grain size in conductors for semiconductor vias and trenches' [patent_app_type] => B1 [patent_app_number] => 09/975032 [patent_app_country] => US [patent_app_date] => 2001-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2993 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/489/06489683.pdf [firstpage_image] =>[orig_patent_app_number] => 09975032 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/975032
Variable grain size in conductors for semiconductor vias and trenches Oct 9, 2001 Issued
Array ( [id] => 6153813 [patent_doc_number] => 20020145156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-10 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/971958 [patent_app_country] => US [patent_app_date] => 2001-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10289 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20020145156.pdf [firstpage_image] =>[orig_patent_app_number] => 09971958 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/971958
Semiconductor device and method for manufacturing the same Oct 8, 2001 Issued
Array ( [id] => 1379177 [patent_doc_number] => 06555450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-29 [patent_title] => 'Contact forming method for semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/971778 [patent_app_country] => US [patent_app_date] => 2001-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 4983 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/555/06555450.pdf [firstpage_image] =>[orig_patent_app_number] => 09971778 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/971778
Contact forming method for semiconductor device Oct 3, 2001 Issued
Array ( [id] => 6237596 [patent_doc_number] => 20020043723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-18 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => new [patent_app_number] => 09/969968 [patent_app_country] => US [patent_app_date] => 2001-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 22450 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20020043723.pdf [firstpage_image] =>[orig_patent_app_number] => 09969968 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/969968
Semiconductor device and manufacturing method thereof Oct 3, 2001 Issued
Array ( [id] => 1390558 [patent_doc_number] => 06544878 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-08 [patent_title] => 'Microelectronic fabrication having formed therein terminal electrode structure providing enhanced barrier properties' [patent_app_type] => B2 [patent_app_number] => 09/970231 [patent_app_country] => US [patent_app_date] => 2001-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 6620 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/544/06544878.pdf [firstpage_image] =>[orig_patent_app_number] => 09970231 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/970231
Microelectronic fabrication having formed therein terminal electrode structure providing enhanced barrier properties Oct 2, 2001 Issued
Array ( [id] => 5936203 [patent_doc_number] => 20020061639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-23 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/966741 [patent_app_country] => US [patent_app_date] => 2001-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13181 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20020061639.pdf [firstpage_image] =>[orig_patent_app_number] => 09966741 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/966741
Semiconductor device and method for manufacturing the same Sep 30, 2001 Abandoned
Array ( [id] => 5814910 [patent_doc_number] => 20020039843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-04 [patent_title] => 'Method of manufacturing a semiconductor integrated circuit device' [patent_app_type] => new [patent_app_number] => 09/964628 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 15115 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20020039843.pdf [firstpage_image] =>[orig_patent_app_number] => 09964628 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/964628
Method of manufacturing a semiconductor integrated circuit device Sep 27, 2001 Issued
Array ( [id] => 6674377 [patent_doc_number] => 20030059980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Copper interconnect barrier layer structure and formation method' [patent_app_type] => new [patent_app_number] => 09/964108 [patent_app_country] => US [patent_app_date] => 2001-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3036 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20030059980.pdf [firstpage_image] =>[orig_patent_app_number] => 09964108 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/964108
Copper interconnect barrier layer structure and formation method Sep 24, 2001 Issued
Array ( [id] => 6447498 [patent_doc_number] => 20020177304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/961358 [patent_app_country] => US [patent_app_date] => 2001-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5543 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20020177304.pdf [firstpage_image] =>[orig_patent_app_number] => 09961358 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/961358
Semiconductor device and method of manufacturing the same Sep 24, 2001 Issued
Array ( [id] => 6395995 [patent_doc_number] => 20020036348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-28 [patent_title] => 'Semiconductor device having multi-layered wiring structure' [patent_app_type] => new [patent_app_number] => 09/961098 [patent_app_country] => US [patent_app_date] => 2001-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8014 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20020036348.pdf [firstpage_image] =>[orig_patent_app_number] => 09961098 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/961098
Semiconductor device having multi-layered wiring structure Sep 23, 2001 Abandoned
Array ( [id] => 6674392 [patent_doc_number] => 20030059995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Deep sub-micron raised source/drain CMOS structure and method of making the same' [patent_app_type] => new [patent_app_number] => 09/963078 [patent_app_country] => US [patent_app_date] => 2001-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1675 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20030059995.pdf [firstpage_image] =>[orig_patent_app_number] => 09963078 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/963078
Deep sub-micron raised source/drain CMOS structure and method of making the same Sep 23, 2001 Abandoned
Array ( [id] => 6720981 [patent_doc_number] => 20030054670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'COMPOSITE MICROELECTRONIC DIELECTRIC LAYER WITH INHIBITED CRACK SUSCEPTIBILITY' [patent_app_type] => new [patent_app_number] => 09/954858 [patent_app_country] => US [patent_app_date] => 2001-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3985 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20030054670.pdf [firstpage_image] =>[orig_patent_app_number] => 09954858 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/954858
Composite microelectronic dielectric layer with inhibited crack susceptibility Sep 16, 2001 Issued
Array ( [id] => 6573363 [patent_doc_number] => 20020014701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-07 [patent_title] => 'Interconnect structure for semiconductor device and method of fabrication' [patent_app_type] => new [patent_app_number] => 09/953152 [patent_app_country] => US [patent_app_date] => 2001-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2017 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20020014701.pdf [firstpage_image] =>[orig_patent_app_number] => 09953152 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/953152
Interconnect structure for semiconductor device and method of fabrication Sep 16, 2001 Abandoned
Array ( [id] => 6285113 [patent_doc_number] => 20020053739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'Semiconductor device and method of fabricating the same' [patent_app_type] => new [patent_app_number] => 09/951508 [patent_app_country] => US [patent_app_date] => 2001-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5600 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20020053739.pdf [firstpage_image] =>[orig_patent_app_number] => 09951508 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/951508
Semiconductor device and method of fabricating the same Sep 13, 2001 Abandoned
Array ( [id] => 1440111 [patent_doc_number] => 06495454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-17 [patent_title] => 'Substrate interconnect for power distribution on integrated circuits' [patent_app_type] => B2 [patent_app_number] => 09/953695 [patent_app_country] => US [patent_app_date] => 2001-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5024 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/495/06495454.pdf [firstpage_image] =>[orig_patent_app_number] => 09953695 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/953695
Substrate interconnect for power distribution on integrated circuits Sep 11, 2001 Issued
Array ( [id] => 7130237 [patent_doc_number] => 20040041266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Semiconductor device and fabrication method therefor' [patent_app_type] => new [patent_app_number] => 10/380038 [patent_app_country] => US [patent_app_date] => 2003-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6595 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20040041266.pdf [firstpage_image] =>[orig_patent_app_number] => 10380038 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/380038
Semiconductor device and fabrication method therefor Sep 10, 2001 Issued
Array ( [id] => 6630900 [patent_doc_number] => 20020086518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Methods for producing electrode and semiconductor device' [patent_app_type] => new [patent_app_number] => 09/950250 [patent_app_country] => US [patent_app_date] => 2001-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3888 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20020086518.pdf [firstpage_image] =>[orig_patent_app_number] => 09950250 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/950250
Methods for producing electrode and semiconductor device Sep 9, 2001 Issued
Array ( [id] => 7645661 [patent_doc_number] => 06472308 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Borderless vias on bottom metal' [patent_app_type] => B1 [patent_app_number] => 09/949276 [patent_app_country] => US [patent_app_date] => 2001-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4802 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/472/06472308.pdf [firstpage_image] =>[orig_patent_app_number] => 09949276 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/949276
Borderless vias on bottom metal Sep 6, 2001 Issued
Array ( [id] => 1155499 [patent_doc_number] => 06764894 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-20 [patent_title] => 'Elevated pore phase-change memory' [patent_app_type] => B2 [patent_app_number] => 09/944478 [patent_app_country] => US [patent_app_date] => 2001-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 1753 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/764/06764894.pdf [firstpage_image] =>[orig_patent_app_number] => 09944478 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/944478
Elevated pore phase-change memory Aug 30, 2001 Issued
Array ( [id] => 6502055 [patent_doc_number] => 20020025604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-28 [patent_title] => 'Low temperature semiconductor layering and three-dimensional electronic circuits using the layering' [patent_app_type] => new [patent_app_number] => 09/943099 [patent_app_country] => US [patent_app_date] => 2001-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3068 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20020025604.pdf [firstpage_image] =>[orig_patent_app_number] => 09943099 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/943099
Low temperature semiconductor layering and three-dimensional electronic circuits using the layering Aug 29, 2001 Issued
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