Search

Barbara J Bullock

Examiner (ID: 9881)

Most Active Art Unit
2901
Art Unit(s)
2900, 2912, 2901, 2902
Total Applications
4468
Issued Applications
4372
Pending Applications
0
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1494754 [patent_doc_number] => 06403395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-06-11 [patent_title] => 'Electro-optical device, method for making the same, and electronic apparatus' [patent_app_type] => B2 [patent_app_number] => 09/939562 [patent_app_country] => US [patent_app_date] => 2001-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 15093 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/403/06403395.pdf [firstpage_image] =>[orig_patent_app_number] => 09939562 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/939562
Electro-optical device, method for making the same, and electronic apparatus Aug 27, 2001 Issued
Array ( [id] => 6063562 [patent_doc_number] => 20020031879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-14 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => new [patent_app_number] => 09/934538 [patent_app_country] => US [patent_app_date] => 2001-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 11291 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20020031879.pdf [firstpage_image] =>[orig_patent_app_number] => 09934538 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/934538
Method for fabricating semiconductor device Aug 22, 2001 Issued
Array ( [id] => 1597202 [patent_doc_number] => 06384482 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Method for forming a dielectric layer in a semiconductor device by using etch stop layers' [patent_app_type] => B1 [patent_app_number] => 09/929098 [patent_app_country] => US [patent_app_date] => 2001-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 1721 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/384/06384482.pdf [firstpage_image] =>[orig_patent_app_number] => 09929098 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/929098
Method for forming a dielectric layer in a semiconductor device by using etch stop layers Aug 14, 2001 Issued
Array ( [id] => 1518937 [patent_doc_number] => 06501141 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Self-aligned contact with improved isolation and method for forming' [patent_app_type] => B1 [patent_app_number] => 09/928839 [patent_app_country] => US [patent_app_date] => 2001-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 1841 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/501/06501141.pdf [firstpage_image] =>[orig_patent_app_number] => 09928839 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/928839
Self-aligned contact with improved isolation and method for forming Aug 12, 2001 Issued
Array ( [id] => 6405873 [patent_doc_number] => 20020037622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-28 [patent_title] => 'Method of forming a contact in an integrated circuit' [patent_app_type] => new [patent_app_number] => 09/923746 [patent_app_country] => US [patent_app_date] => 2001-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4574 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20020037622.pdf [firstpage_image] =>[orig_patent_app_number] => 09923746 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/923746
Contact in an integrated circuit Aug 6, 2001 Issued
Array ( [id] => 1270297 [patent_doc_number] => 06653220 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-25 [patent_title] => 'Advance metallization process' [patent_app_type] => B2 [patent_app_number] => 09/922523 [patent_app_country] => US [patent_app_date] => 2001-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2055 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/653/06653220.pdf [firstpage_image] =>[orig_patent_app_number] => 09922523 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/922523
Advance metallization process Aug 2, 2001 Issued
Array ( [id] => 1495065 [patent_doc_number] => 06403476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-06-11 [patent_title] => 'Semiconductor chip, semiconductor wafer, semiconductor device and method of manufacturing the semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/917208 [patent_app_country] => US [patent_app_date] => 2001-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3656 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/403/06403476.pdf [firstpage_image] =>[orig_patent_app_number] => 09917208 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/917208
Semiconductor chip, semiconductor wafer, semiconductor device and method of manufacturing the semiconductor device Jul 29, 2001 Issued
Array ( [id] => 1595706 [patent_doc_number] => 06492259 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-10 [patent_title] => 'Process for making a planar integrated circuit interconnect' [patent_app_type] => B2 [patent_app_number] => 09/909402 [patent_app_country] => US [patent_app_date] => 2001-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3144 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/492/06492259.pdf [firstpage_image] =>[orig_patent_app_number] => 09909402 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/909402
Process for making a planar integrated circuit interconnect Jul 18, 2001 Issued
Array ( [id] => 1404288 [patent_doc_number] => 06541862 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-01 [patent_title] => 'Semiconductor device including a plurality of interconnection layers, manufacturing method thereof and method of designing semiconductor circuit used in the manufacturing method' [patent_app_type] => B2 [patent_app_number] => 09/907675 [patent_app_country] => US [patent_app_date] => 2001-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 11584 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/541/06541862.pdf [firstpage_image] =>[orig_patent_app_number] => 09907675 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/907675
Semiconductor device including a plurality of interconnection layers, manufacturing method thereof and method of designing semiconductor circuit used in the manufacturing method Jul 18, 2001 Issued
Array ( [id] => 5885888 [patent_doc_number] => 20020011672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-31 [patent_title] => 'Semiconductor device and semiconductor device manufacturing method' [patent_app_type] => new [patent_app_number] => 09/904869 [patent_app_country] => US [patent_app_date] => 2001-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 14980 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20020011672.pdf [firstpage_image] =>[orig_patent_app_number] => 09904869 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/904869
Semiconductor device and semiconductor device manufacturing method Jul 15, 2001 Issued
Array ( [id] => 1396725 [patent_doc_number] => 06531366 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'Method and structure for high-voltage device with self-aligned graded junctions' [patent_app_type] => B1 [patent_app_number] => 09/904328 [patent_app_country] => US [patent_app_date] => 2001-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 6052 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/531/06531366.pdf [firstpage_image] =>[orig_patent_app_number] => 09904328 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/904328
Method and structure for high-voltage device with self-aligned graded junctions Jul 11, 2001 Issued
Array ( [id] => 1518807 [patent_doc_number] => 06501113 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-31 [patent_title] => 'Semiconductor device with capacitor using high dielectric constant film or ferroelectric film' [patent_app_type] => B2 [patent_app_number] => 09/897038 [patent_app_country] => US [patent_app_date] => 2001-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 28 [patent_no_of_words] => 8967 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/501/06501113.pdf [firstpage_image] =>[orig_patent_app_number] => 09897038 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/897038
Semiconductor device with capacitor using high dielectric constant film or ferroelectric film Jul 2, 2001 Issued
Array ( [id] => 6755857 [patent_doc_number] => 20030003634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'UTILIZING ATOMIC LAYER DEPOSITION FOR PROGRAMMABLE DEVICE' [patent_app_type] => new [patent_app_number] => 09/896529 [patent_app_country] => US [patent_app_date] => 2001-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4059 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20030003634.pdf [firstpage_image] =>[orig_patent_app_number] => 09896529 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/896529
Utilizing atomic layer deposition for programmable device Jun 29, 2001 Issued
Array ( [id] => 1545368 [patent_doc_number] => 06444565 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Dual-rie structure for via/line interconnections' [patent_app_type] => B1 [patent_app_number] => 09/896204 [patent_app_country] => US [patent_app_date] => 2001-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 24 [patent_no_of_words] => 4467 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/444/06444565.pdf [firstpage_image] =>[orig_patent_app_number] => 09896204 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/896204
Dual-rie structure for via/line interconnections Jun 28, 2001 Issued
Array ( [id] => 944353 [patent_doc_number] => 06967407 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-22 [patent_title] => 'Semiconductor device and method of manufacturing the semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/333838 [patent_app_country] => US [patent_app_date] => 2001-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 15088 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/967/06967407.pdf [firstpage_image] =>[orig_patent_app_number] => 10333838 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/333838
Semiconductor device and method of manufacturing the semiconductor device Jun 24, 2001 Issued
Array ( [id] => 1477599 [patent_doc_number] => 06344377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-02-05 [patent_title] => 'Liquid crystal display and method of manufacturing the same' [patent_app_type] => B2 [patent_app_number] => 09/880829 [patent_app_country] => US [patent_app_date] => 2001-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 5618 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/344/06344377.pdf [firstpage_image] =>[orig_patent_app_number] => 09880829 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/880829
Liquid crystal display and method of manufacturing the same Jun 14, 2001 Issued
Array ( [id] => 6920628 [patent_doc_number] => 20010028113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-11 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => new [patent_app_number] => 09/876044 [patent_app_country] => US [patent_app_date] => 2001-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13534 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20010028113.pdf [firstpage_image] =>[orig_patent_app_number] => 09876044 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/876044
Method of manufacturing semiconductor device Jun 7, 2001 Issued
Array ( [id] => 7323484 [patent_doc_number] => 20040251536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-16 [patent_title] => 'Semiconductor device' [patent_app_type] => new [patent_app_number] => 10/332809 [patent_app_country] => US [patent_app_date] => 2003-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5005 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0251/20040251536.pdf [firstpage_image] =>[orig_patent_app_number] => 10332809 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/332809
Semiconductor device May 31, 2001 Issued
Array ( [id] => 6615883 [patent_doc_number] => 20020016016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-07 [patent_title] => 'Process for producing a photovoltaic element' [patent_app_type] => new [patent_app_number] => 09/870659 [patent_app_country] => US [patent_app_date] => 2001-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9177 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20020016016.pdf [firstpage_image] =>[orig_patent_app_number] => 09870659 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/870659
Process for producing a photovoltaic element May 31, 2001 Issued
Array ( [id] => 1516217 [patent_doc_number] => 06420778 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Differential electrical transmission line structures employing crosstalk compensation and related methods' [patent_app_type] => B1 [patent_app_number] => 09/872569 [patent_app_country] => US [patent_app_date] => 2001-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3378 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/420/06420778.pdf [firstpage_image] =>[orig_patent_app_number] => 09872569 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/872569
Differential electrical transmission line structures employing crosstalk compensation and related methods May 31, 2001 Issued
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