Search

Barbara J Bullock

Examiner (ID: 9881)

Most Active Art Unit
2901
Art Unit(s)
2900, 2912, 2901, 2902
Total Applications
4468
Issued Applications
4372
Pending Applications
0
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1503639 [patent_doc_number] => 06465341 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Manufacturing method for semiconductor interconnect barrier of boron silicon nitride' [patent_app_type] => B1 [patent_app_number] => 09/872465 [patent_app_country] => US [patent_app_date] => 2001-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2583 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/465/06465341.pdf [firstpage_image] =>[orig_patent_app_number] => 09872465 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/872465
Manufacturing method for semiconductor interconnect barrier of boron silicon nitride May 30, 2001 Issued
09/856978 Method of forming tungsten silicide film, and method of fabricating metal-insulator-semiconductor type transistor May 29, 2001 Abandoned
Array ( [id] => 6123585 [patent_doc_number] => 20020074660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'Semiconductor device having a multiple layer wiring structure, wiring method, wiring device, and recording medium' [patent_app_type] => new [patent_app_number] => 09/855590 [patent_app_country] => US [patent_app_date] => 2001-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7676 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20020074660.pdf [firstpage_image] =>[orig_patent_app_number] => 09855590 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/855590
Semiconductor device having a multiple layer wiring structure, wiring method, wiring device, and recording medium May 15, 2001 Abandoned
Array ( [id] => 1503440 [patent_doc_number] => 06465300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-15 [patent_title] => 'Method for forming a lower electrode for use in a semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/855848 [patent_app_country] => US [patent_app_date] => 2001-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1462 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/465/06465300.pdf [firstpage_image] =>[orig_patent_app_number] => 09855848 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/855848
Method for forming a lower electrode for use in a semiconductor device May 15, 2001 Issued
Array ( [id] => 6237579 [patent_doc_number] => 20020043715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-18 [patent_title] => 'Semiconductor device with dummy wiring layers' [patent_app_type] => new [patent_app_number] => 09/845819 [patent_app_country] => US [patent_app_date] => 2001-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3369 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20020043715.pdf [firstpage_image] =>[orig_patent_app_number] => 09845819 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/845819
Semiconductor device with dummy wiring layers Apr 29, 2001 Issued
Array ( [id] => 7064988 [patent_doc_number] => 20010044199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-22 [patent_title] => 'Semiconductor device and manufacture thereof' [patent_app_type] => new [patent_app_number] => 09/838923 [patent_app_country] => US [patent_app_date] => 2001-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4914 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20010044199.pdf [firstpage_image] =>[orig_patent_app_number] => 09838923 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/838923
Semiconductor device and manufacture thereof Apr 19, 2001 Abandoned
Array ( [id] => 1440115 [patent_doc_number] => 06495455 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-17 [patent_title] => 'Method for enhancing selectivity between a film of a light-sensitive material and a layer to be etched in electronic semiconductor device fabrication processes' [patent_app_type] => B2 [patent_app_number] => 09/836937 [patent_app_country] => US [patent_app_date] => 2001-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2666 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/495/06495455.pdf [firstpage_image] =>[orig_patent_app_number] => 09836937 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/836937
Method for enhancing selectivity between a film of a light-sensitive material and a layer to be etched in electronic semiconductor device fabrication processes Apr 16, 2001 Issued
Array ( [id] => 1346534 [patent_doc_number] => 06583042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-24 [patent_title] => 'Semiconductor method of making electrical connection between an electrically conductive line and a node location, and integrated circuitry' [patent_app_type] => B2 [patent_app_number] => 09/824897 [patent_app_country] => US [patent_app_date] => 2001-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2989 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/583/06583042.pdf [firstpage_image] =>[orig_patent_app_number] => 09824897 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/824897
Semiconductor method of making electrical connection between an electrically conductive line and a node location, and integrated circuitry Apr 1, 2001 Issued
Array ( [id] => 1549594 [patent_doc_number] => 06346432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-02-12 [patent_title] => 'Semiconductor element having external connection terminals, method of manufacturing the semiconductor element, and semiconductor device equipped with the semiconductor element' [patent_app_type] => B2 [patent_app_number] => 09/803027 [patent_app_country] => US [patent_app_date] => 2001-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 6584 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/346/06346432.pdf [firstpage_image] =>[orig_patent_app_number] => 09803027 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/803027
Semiconductor element having external connection terminals, method of manufacturing the semiconductor element, and semiconductor device equipped with the semiconductor element Mar 11, 2001 Issued
Array ( [id] => 6882704 [patent_doc_number] => 20010049176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-06 [patent_title] => 'Method of forming low-resistivity connections in non-volatile memories' [patent_app_type] => new [patent_app_number] => 09/798778 [patent_app_country] => US [patent_app_date] => 2001-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2661 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20010049176.pdf [firstpage_image] =>[orig_patent_app_number] => 09798778 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/798778
Method of forming low-resistivity connections in non-volatile memories Mar 1, 2001 Issued
Array ( [id] => 1246732 [patent_doc_number] => 06677680 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-13 [patent_title] => 'Hybrid low-k interconnect structure comprised of 2 spin-on dielectric materials' [patent_app_type] => B2 [patent_app_number] => 09/795429 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4270 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/677/06677680.pdf [firstpage_image] =>[orig_patent_app_number] => 09795429 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/795429
Hybrid low-k interconnect structure comprised of 2 spin-on dielectric materials Feb 27, 2001 Issued
Array ( [id] => 6900131 [patent_doc_number] => 20010009807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-26 [patent_title] => 'Small grain size, conformal aluminum interconnects and method for their formation' [patent_app_type] => new [patent_app_number] => 09/782441 [patent_app_country] => US [patent_app_date] => 2001-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3225 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20010009807.pdf [firstpage_image] =>[orig_patent_app_number] => 09782441 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/782441
Small grain size, conformal aluminum interconnects and method for their formation Feb 12, 2001 Issued
Array ( [id] => 1150381 [patent_doc_number] => 06774487 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-10 [patent_title] => 'Small grain size, conformal aluminum interconnects and method for their formation' [patent_app_type] => B2 [patent_app_number] => 09/782498 [patent_app_country] => US [patent_app_date] => 2001-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3221 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/774/06774487.pdf [firstpage_image] =>[orig_patent_app_number] => 09782498 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/782498
Small grain size, conformal aluminum interconnects and method for their formation Feb 12, 2001 Issued
Array ( [id] => 6033042 [patent_doc_number] => 20020019129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-14 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/779629 [patent_app_country] => US [patent_app_date] => 2001-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5305 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20020019129.pdf [firstpage_image] =>[orig_patent_app_number] => 09779629 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/779629
Semiconductor device and method of manufacturing the same Feb 8, 2001 Issued
Array ( [id] => 1505513 [patent_doc_number] => 06465889 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Silicon carbide barc in dual damascene processing' [patent_app_type] => B1 [patent_app_number] => 09/778109 [patent_app_country] => US [patent_app_date] => 2001-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3689 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/465/06465889.pdf [firstpage_image] =>[orig_patent_app_number] => 09778109 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/778109
Silicon carbide barc in dual damascene processing Feb 6, 2001 Issued
Array ( [id] => 6960461 [patent_doc_number] => 20010012225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-09 [patent_title] => 'CMOS imager with selectively silicided gates' [patent_app_type] => new [patent_app_number] => 09/777890 [patent_app_country] => US [patent_app_date] => 2001-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7521 [patent_no_of_claims] => 86 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20010012225.pdf [firstpage_image] =>[orig_patent_app_number] => 09777890 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/777890
CMOS imager with selectively silicided gates Feb 6, 2001 Issued
Array ( [id] => 1503638 [patent_doc_number] => 06465340 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Via filled dual damascene structure with middle stop layer and method for making the same' [patent_app_type] => B1 [patent_app_number] => 09/776734 [patent_app_country] => US [patent_app_date] => 2001-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 4231 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/465/06465340.pdf [firstpage_image] =>[orig_patent_app_number] => 09776734 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/776734
Via filled dual damascene structure with middle stop layer and method for making the same Feb 5, 2001 Issued
Array ( [id] => 6959419 [patent_doc_number] => 20010011638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-09 [patent_title] => 'Method of forming a metal seed layer for subsequent plating' [patent_app_type] => new [patent_app_number] => 09/753548 [patent_app_country] => US [patent_app_date] => 2001-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3280 [patent_no_of_claims] => 111 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20010011638.pdf [firstpage_image] =>[orig_patent_app_number] => 09753548 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/753548
Method of forming a metal seed layer for subsequent plating Jan 3, 2001 Issued
Array ( [id] => 1544380 [patent_doc_number] => 06373136 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Damascene wiring structure and semiconductor device with damascene wirings' [patent_app_type] => B1 [patent_app_number] => 09/735478 [patent_app_country] => US [patent_app_date] => 2000-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 47 [patent_no_of_words] => 9650 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373136.pdf [firstpage_image] =>[orig_patent_app_number] => 09735478 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/735478
Damascene wiring structure and semiconductor device with damascene wirings Dec 13, 2000 Issued
Array ( [id] => 1550392 [patent_doc_number] => 06399467 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Method of salicide formation' [patent_app_type] => B1 [patent_app_number] => 09/733779 [patent_app_country] => US [patent_app_date] => 2000-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2080 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/399/06399467.pdf [firstpage_image] =>[orig_patent_app_number] => 09733779 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/733779
Method of salicide formation Dec 7, 2000 Issued
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