Search

Barbara J Bullock

Examiner (ID: 9881)

Most Active Art Unit
2901
Art Unit(s)
2900, 2912, 2901, 2902
Total Applications
4468
Issued Applications
4372
Pending Applications
0
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1468627 [patent_doc_number] => 06459155 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Damascene processing employing low Si-SiON etch stop layer/arc' [patent_app_type] => B1 [patent_app_number] => 09/729528 [patent_app_country] => US [patent_app_date] => 2000-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3098 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/459/06459155.pdf [firstpage_image] =>[orig_patent_app_number] => 09729528 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/729528
Damascene processing employing low Si-SiON etch stop layer/arc Dec 4, 2000 Issued
Array ( [id] => 7644007 [patent_doc_number] => 06429031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-08-06 [patent_title] => 'Method for forming wiring pattern of a semiconductor integrated circuit' [patent_app_type] => B2 [patent_app_number] => 09/725268 [patent_app_country] => US [patent_app_date] => 2000-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 4773 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/429/06429031.pdf [firstpage_image] =>[orig_patent_app_number] => 09725268 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/725268
Method for forming wiring pattern of a semiconductor integrated circuit Nov 28, 2000 Issued
Array ( [id] => 1478173 [patent_doc_number] => 06451687 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Intermetal dielectric layer for integrated circuits' [patent_app_type] => B1 [patent_app_number] => 09/721898 [patent_app_country] => US [patent_app_date] => 2000-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 1938 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/451/06451687.pdf [firstpage_image] =>[orig_patent_app_number] => 09721898 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/721898
Intermetal dielectric layer for integrated circuits Nov 23, 2000 Issued
Array ( [id] => 1494844 [patent_doc_number] => 06403419 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Method of manufacturing a flash memory device' [patent_app_type] => B1 [patent_app_number] => 09/717049 [patent_app_country] => US [patent_app_date] => 2000-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 2929 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/403/06403419.pdf [firstpage_image] =>[orig_patent_app_number] => 09717049 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/717049
Method of manufacturing a flash memory device Nov 21, 2000 Issued
Array ( [id] => 1371330 [patent_doc_number] => 06562667 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'TFT for LCD device and fabrication method thereof' [patent_app_type] => B1 [patent_app_number] => 09/715188 [patent_app_country] => US [patent_app_date] => 2000-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 2686 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/562/06562667.pdf [firstpage_image] =>[orig_patent_app_number] => 09715188 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/715188
TFT for LCD device and fabrication method thereof Nov 19, 2000 Issued
Array ( [id] => 1517367 [patent_doc_number] => 06500757 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Method and apparatus for controlling grain growth roughening in conductive stacks' [patent_app_type] => B1 [patent_app_number] => 09/705938 [patent_app_country] => US [patent_app_date] => 2000-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2279 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/500/06500757.pdf [firstpage_image] =>[orig_patent_app_number] => 09705938 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/705938
Method and apparatus for controlling grain growth roughening in conductive stacks Nov 2, 2000 Issued
Array ( [id] => 961084 [patent_doc_number] => 06951797 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-10-04 [patent_title] => 'Method relating to anodic bonding' [patent_app_type] => utility [patent_app_number] => 10/111138 [patent_app_country] => US [patent_app_date] => 2000-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 1916 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/951/06951797.pdf [firstpage_image] =>[orig_patent_app_number] => 10111138 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/111138
Method relating to anodic bonding Oct 16, 2000 Issued
Array ( [id] => 1597975 [patent_doc_number] => 06492729 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Configuration and method for connecting conductor tracks' [patent_app_type] => B1 [patent_app_number] => 09/685659 [patent_app_country] => US [patent_app_date] => 2000-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1968 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/492/06492729.pdf [firstpage_image] =>[orig_patent_app_number] => 09685659 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/685659
Configuration and method for connecting conductor tracks Oct 9, 2000 Issued
Array ( [id] => 4381299 [patent_doc_number] => 06294434 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Method of forming a metal silicide layer on a polysilicon gate structure and on a source/drain region of a MOSFET device' [patent_app_type] => 1 [patent_app_number] => 9/670379 [patent_app_country] => US [patent_app_date] => 2000-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1904 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/294/06294434.pdf [firstpage_image] =>[orig_patent_app_number] => 670379 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/670379
Method of forming a metal silicide layer on a polysilicon gate structure and on a source/drain region of a MOSFET device Sep 26, 2000 Issued
Array ( [id] => 1410877 [patent_doc_number] => 06534867 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Semiconductor device, semiconductor element and method for producing same' [patent_app_type] => B1 [patent_app_number] => 09/670990 [patent_app_country] => US [patent_app_date] => 2000-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 78 [patent_figures_cnt] => 224 [patent_no_of_words] => 17095 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/534/06534867.pdf [firstpage_image] =>[orig_patent_app_number] => 09670990 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/670990
Semiconductor device, semiconductor element and method for producing same Sep 25, 2000 Issued
Array ( [id] => 1561076 [patent_doc_number] => 06362042 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'DRAM having a cup-shaped storage node electrode recessed within an insulating layer' [patent_app_type] => B1 [patent_app_number] => 09/664773 [patent_app_country] => US [patent_app_date] => 2000-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 22 [patent_no_of_words] => 8339 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362042.pdf [firstpage_image] =>[orig_patent_app_number] => 09664773 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/664773
DRAM having a cup-shaped storage node electrode recessed within an insulating layer Sep 18, 2000 Issued
Array ( [id] => 1537229 [patent_doc_number] => 06337519 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-08 [patent_title] => 'Semiconductor device having a multilayered interconnection structure' [patent_app_type] => B1 [patent_app_number] => 09/662318 [patent_app_country] => US [patent_app_date] => 2000-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 28 [patent_no_of_words] => 4551 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/337/06337519.pdf [firstpage_image] =>[orig_patent_app_number] => 09662318 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/662318
Semiconductor device having a multilayered interconnection structure Sep 13, 2000 Issued
Array ( [id] => 4351037 [patent_doc_number] => 06291344 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Integrated circuit with improved contact barrier' [patent_app_type] => 1 [patent_app_number] => 9/660738 [patent_app_country] => US [patent_app_date] => 2000-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 6195 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291344.pdf [firstpage_image] =>[orig_patent_app_number] => 660738 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/660738
Integrated circuit with improved contact barrier Sep 12, 2000 Issued
Array ( [id] => 4270482 [patent_doc_number] => 06323048 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Integrated circuit probe pad metal level' [patent_app_type] => 1 [patent_app_number] => 9/652618 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3375 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323048.pdf [firstpage_image] =>[orig_patent_app_number] => 652618 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/652618
Integrated circuit probe pad metal level Aug 30, 2000 Issued
Array ( [id] => 1480503 [patent_doc_number] => 06452223 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Methods of fabricating buried digit lines and semiconductor devices including same' [patent_app_type] => B1 [patent_app_number] => 09/651861 [patent_app_country] => US [patent_app_date] => 2000-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 4896 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/452/06452223.pdf [firstpage_image] =>[orig_patent_app_number] => 09651861 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/651861
Methods of fabricating buried digit lines and semiconductor devices including same Aug 29, 2000 Issued
Array ( [id] => 1542717 [patent_doc_number] => 06372629 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Methods of fabricating buried digit lines and semiconductor devices including same' [patent_app_type] => B1 [patent_app_number] => 09/650797 [patent_app_country] => US [patent_app_date] => 2000-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 4915 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/372/06372629.pdf [firstpage_image] =>[orig_patent_app_number] => 09650797 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/650797
Methods of fabricating buried digit lines and semiconductor devices including same Aug 29, 2000 Issued
Array ( [id] => 1126655 [patent_doc_number] => 06790762 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-14 [patent_title] => 'Method of making an electrical device including an interconnect structure' [patent_app_type] => B1 [patent_app_number] => 09/651386 [patent_app_country] => US [patent_app_date] => 2000-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4937 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/790/06790762.pdf [firstpage_image] =>[orig_patent_app_number] => 09651386 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/651386
Method of making an electrical device including an interconnect structure Aug 28, 2000 Issued
Array ( [id] => 4270906 [patent_doc_number] => 06323076 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Integrated circuit having temporary conductive path structure and method for forming the same' [patent_app_type] => 1 [patent_app_number] => 9/649342 [patent_app_country] => US [patent_app_date] => 2000-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4873 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323076.pdf [firstpage_image] =>[orig_patent_app_number] => 649342 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/649342
Integrated circuit having temporary conductive path structure and method for forming the same Aug 27, 2000 Issued
Array ( [id] => 4292819 [patent_doc_number] => 06268656 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Method and structure for uniform height solder bumps on a semiconductor wafer' [patent_app_type] => 1 [patent_app_number] => 9/639139 [patent_app_country] => US [patent_app_date] => 2000-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3698 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268656.pdf [firstpage_image] =>[orig_patent_app_number] => 639139 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/639139
Method and structure for uniform height solder bumps on a semiconductor wafer Aug 14, 2000 Issued
Array ( [id] => 1421421 [patent_doc_number] => 06522011 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'Low capacitance wiring layout and method for making same' [patent_app_type] => B1 [patent_app_number] => 09/638390 [patent_app_country] => US [patent_app_date] => 2000-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 31 [patent_no_of_words] => 4923 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/522/06522011.pdf [firstpage_image] =>[orig_patent_app_number] => 09638390 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/638390
Low capacitance wiring layout and method for making same Aug 14, 2000 Issued
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