Barbara J Bullock
Examiner (ID: 9881)
Most Active Art Unit | 2901 |
Art Unit(s) | 2900, 2912, 2901, 2902 |
Total Applications | 4468 |
Issued Applications | 4372 |
Pending Applications | 0 |
Abandoned Applications | 96 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 1468627
[patent_doc_number] => 06459155
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-01
[patent_title] => 'Damascene processing employing low Si-SiON etch stop layer/arc'
[patent_app_type] => B1
[patent_app_number] => 09/729528
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Array
(
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[patent_doc_number] => 06429031
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[patent_kind] => B2
[patent_issue_date] => 2002-08-06
[patent_title] => 'Method for forming wiring pattern of a semiconductor integrated circuit'
[patent_app_type] => B2
[patent_app_number] => 09/725268
[patent_app_country] => US
[patent_app_date] => 2000-11-29
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Array
(
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[patent_kind] => B1
[patent_issue_date] => 2002-09-17
[patent_title] => 'Intermetal dielectric layer for integrated circuits'
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[patent_app_number] => 09/721898
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/721898 | Intermetal dielectric layer for integrated circuits | Nov 23, 2000 | Issued |
Array
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[patent_issue_date] => 2002-06-11
[patent_title] => 'Method of manufacturing a flash memory device'
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[patent_app_number] => 09/717049
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Array
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[patent_issue_date] => 2003-05-13
[patent_title] => 'TFT for LCD device and fabrication method thereof'
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Array
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[patent_issue_date] => 2002-12-31
[patent_title] => 'Method and apparatus for controlling grain growth roughening in conductive stacks'
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Array
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[patent_title] => 'Method relating to anodic bonding'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/111138 | Method relating to anodic bonding | Oct 16, 2000 | Issued |
Array
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[patent_doc_number] => 06492729
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[patent_issue_date] => 2002-12-10
[patent_title] => 'Configuration and method for connecting conductor tracks'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/685659 | Configuration and method for connecting conductor tracks | Oct 9, 2000 | Issued |
Array
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[id] => 4381299
[patent_doc_number] => 06294434
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-25
[patent_title] => 'Method of forming a metal silicide layer on a polysilicon gate structure and on a source/drain region of a MOSFET device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/670379 | Method of forming a metal silicide layer on a polysilicon gate structure and on a source/drain region of a MOSFET device | Sep 26, 2000 | Issued |
Array
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[id] => 1410877
[patent_doc_number] => 06534867
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[patent_issue_date] => 2003-03-18
[patent_title] => 'Semiconductor device, semiconductor element and method for producing same'
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[patent_app_number] => 09/670990
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Array
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[id] => 1561076
[patent_doc_number] => 06362042
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[patent_title] => 'DRAM having a cup-shaped storage node electrode recessed within an insulating layer'
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Array
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Array
(
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Array
(
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[patent_title] => 'Integrated circuit probe pad metal level'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/652618 | Integrated circuit probe pad metal level | Aug 30, 2000 | Issued |
Array
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Array
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Array
(
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Array
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Array
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