Barbara J Bullock
Examiner (ID: 9881)
Most Active Art Unit | 2901 |
Art Unit(s) | 2900, 2912, 2901, 2902 |
Total Applications | 4468 |
Issued Applications | 4372 |
Pending Applications | 0 |
Abandoned Applications | 96 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 4275834
[patent_doc_number] => 06281109
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-28
[patent_title] => 'Advance metallization process'
[patent_app_type] => 1
[patent_app_number] => 9/571074
[patent_app_country] => US
[patent_app_date] => 2000-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 2000
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 207
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/281/06281109.pdf
[firstpage_image] =>[orig_patent_app_number] => 571074
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/571074 | Advance metallization process | May 14, 2000 | Issued |
09/568038 | Interconnect structure for semiconductor device and method of fabrication | May 9, 2000 | Abandoned |
Array
(
[id] => 1522329
[patent_doc_number] => 06414392
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-02
[patent_title] => 'Integrated circuit contact'
[patent_app_type] => B1
[patent_app_number] => 09/569578
[patent_app_country] => US
[patent_app_date] => 2000-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 2360
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/414/06414392.pdf
[firstpage_image] =>[orig_patent_app_number] => 09569578
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/569578 | Integrated circuit contact | May 9, 2000 | Issued |
Array
(
[id] => 4318187
[patent_doc_number] => 06316831
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-13
[patent_title] => 'Microelectronic fabrication having formed therein terminal electrode structure providing enhanced barrier properties'
[patent_app_type] => 1
[patent_app_number] => 9/564589
[patent_app_country] => US
[patent_app_date] => 2000-05-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 6428
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/316/06316831.pdf
[firstpage_image] =>[orig_patent_app_number] => 564589
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/564589 | Microelectronic fabrication having formed therein terminal electrode structure providing enhanced barrier properties | May 4, 2000 | Issued |
Array
(
[id] => 4387602
[patent_doc_number] => 06294832
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-25
[patent_title] => 'Semiconductor device having structure of copper interconnect/barrier dielectric liner/low-k dielectric trench and its fabrication method'
[patent_app_type] => 1
[patent_app_number] => 9/546539
[patent_app_country] => US
[patent_app_date] => 2000-04-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 3491
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/294/06294832.pdf
[firstpage_image] =>[orig_patent_app_number] => 546539
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/546539 | Semiconductor device having structure of copper interconnect/barrier dielectric liner/low-k dielectric trench and its fabrication method | Apr 9, 2000 | Issued |
Array
(
[id] => 1435908
[patent_doc_number] => 06355551
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-03-12
[patent_title] => 'Integrated circuit having a void between adjacent conductive lines'
[patent_app_type] => B1
[patent_app_number] => 09/531879
[patent_app_country] => US
[patent_app_date] => 2000-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 3362
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/355/06355551.pdf
[firstpage_image] =>[orig_patent_app_number] => 09531879
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/531879 | Integrated circuit having a void between adjacent conductive lines | Mar 20, 2000 | Issued |
Array
(
[id] => 1446541
[patent_doc_number] => 06368903
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-09
[patent_title] => 'SOI low capacitance body contact'
[patent_app_type] => B1
[patent_app_number] => 09/527858
[patent_app_country] => US
[patent_app_date] => 2000-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 4057
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/368/06368903.pdf
[firstpage_image] =>[orig_patent_app_number] => 09527858
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/527858 | SOI low capacitance body contact | Mar 16, 2000 | Issued |
Array
(
[id] => 1491880
[patent_doc_number] => 06417568
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-09
[patent_title] => 'Semiconductor device'
[patent_app_type] => B1
[patent_app_number] => 09/522908
[patent_app_country] => US
[patent_app_date] => 2000-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2789
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/417/06417568.pdf
[firstpage_image] =>[orig_patent_app_number] => 09522908
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/522908 | Semiconductor device | Mar 9, 2000 | Issued |
Array
(
[id] => 1172767
[patent_doc_number] => 06750137
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-06-15
[patent_title] => 'Method and apparatus for forming an interlayer insulating film and semiconductor device'
[patent_app_type] => B1
[patent_app_number] => 09/519599
[patent_app_country] => US
[patent_app_date] => 2000-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 36
[patent_no_of_words] => 7210
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/750/06750137.pdf
[firstpage_image] =>[orig_patent_app_number] => 09519599
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/519599 | Method and apparatus for forming an interlayer insulating film and semiconductor device | Mar 5, 2000 | Issued |
Array
(
[id] => 4381522
[patent_doc_number] => 06294450
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-25
[patent_title] => 'Nanoscale patterning for the formation of extensive wires'
[patent_app_type] => 1
[patent_app_number] => 9/516989
[patent_app_country] => US
[patent_app_date] => 2000-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 8
[patent_no_of_words] => 2746
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/294/06294450.pdf
[firstpage_image] =>[orig_patent_app_number] => 516989
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/516989 | Nanoscale patterning for the formation of extensive wires | Feb 29, 2000 | Issued |
Array
(
[id] => 4318970
[patent_doc_number] => 06248655
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-19
[patent_title] => 'Method of fabricating a surface shape recognition sensor'
[patent_app_type] => 1
[patent_app_number] => 9/515962
[patent_app_country] => US
[patent_app_date] => 2000-02-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 79
[patent_no_of_words] => 24891
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/248/06248655.pdf
[firstpage_image] =>[orig_patent_app_number] => 515962
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/515962 | Method of fabricating a surface shape recognition sensor | Feb 28, 2000 | Issued |
Array
(
[id] => 4423686
[patent_doc_number] => 06177715
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-23
[patent_title] => 'Integrated circuit having a level of metallization of variable thickness'
[patent_app_type] => 1
[patent_app_number] => 9/486149
[patent_app_country] => US
[patent_app_date] => 2000-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 12
[patent_no_of_words] => 1713
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/177/06177715.pdf
[firstpage_image] =>[orig_patent_app_number] => 486149
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/486149 | Integrated circuit having a level of metallization of variable thickness | Feb 21, 2000 | Issued |
Array
(
[id] => 1583095
[patent_doc_number] => 06424042
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-23
[patent_title] => 'Semiconductor device and manufacturing method thereof'
[patent_app_type] => B1
[patent_app_number] => 09/505990
[patent_app_country] => US
[patent_app_date] => 2000-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 52
[patent_no_of_words] => 7623
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/424/06424042.pdf
[firstpage_image] =>[orig_patent_app_number] => 09505990
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/505990 | Semiconductor device and manufacturing method thereof | Feb 16, 2000 | Issued |
Array
(
[id] => 7640286
[patent_doc_number] => 06395628
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-28
[patent_title] => 'Contact/via force fill techniques'
[patent_app_type] => B1
[patent_app_number] => 09/506206
[patent_app_country] => US
[patent_app_date] => 2000-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 4095
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 20
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/395/06395628.pdf
[firstpage_image] =>[orig_patent_app_number] => 09506206
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/506206 | Contact/via force fill techniques | Feb 16, 2000 | Issued |
Array
(
[id] => 1459561
[patent_doc_number] => 06391778
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-21
[patent_title] => 'Contact/via force fill techniques and resulting structures'
[patent_app_type] => B1
[patent_app_number] => 09/505607
[patent_app_country] => US
[patent_app_date] => 2000-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 4099
[patent_no_of_claims] => 46
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/391/06391778.pdf
[firstpage_image] =>[orig_patent_app_number] => 09505607
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/505607 | Contact/via force fill techniques and resulting structures | Feb 16, 2000 | Issued |
Array
(
[id] => 963652
[patent_doc_number] => 06949464
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-09-27
[patent_title] => 'Contact/via force fill techniques'
[patent_app_type] => utility
[patent_app_number] => 09/506204
[patent_app_country] => US
[patent_app_date] => 2000-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 4117
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/949/06949464.pdf
[firstpage_image] =>[orig_patent_app_number] => 09506204
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/506204 | Contact/via force fill techniques | Feb 16, 2000 | Issued |
Array
(
[id] => 1532605
[patent_doc_number] => 06410427
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-25
[patent_title] => 'Metal silicidation methods and methods for using same'
[patent_app_type] => B1
[patent_app_number] => 09/491113
[patent_app_country] => US
[patent_app_date] => 2000-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 36
[patent_no_of_words] => 8151
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/410/06410427.pdf
[firstpage_image] =>[orig_patent_app_number] => 09491113
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/491113 | Metal silicidation methods and methods for using same | Jan 24, 2000 | Issued |
Array
(
[id] => 4373603
[patent_doc_number] => 06274934
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-14
[patent_title] => 'Semiconductor device and method of manufacturing thereof'
[patent_app_type] => 1
[patent_app_number] => 9/488778
[patent_app_country] => US
[patent_app_date] => 2000-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 7117
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 209
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/274/06274934.pdf
[firstpage_image] =>[orig_patent_app_number] => 488778
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/488778 | Semiconductor device and method of manufacturing thereof | Jan 20, 2000 | Issued |
Array
(
[id] => 4337231
[patent_doc_number] => 06313538
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-06
[patent_title] => 'Semiconductor device with partial passivation layer'
[patent_app_type] => 1
[patent_app_number] => 9/489479
[patent_app_country] => US
[patent_app_date] => 2000-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 1960
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/313/06313538.pdf
[firstpage_image] =>[orig_patent_app_number] => 489479
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/489479 | Semiconductor device with partial passivation layer | Jan 20, 2000 | Issued |
Array
(
[id] => 4406958
[patent_doc_number] => 06238961
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-29
[patent_title] => 'Semiconductor integrated circuit device and process for manufacturing the same'
[patent_app_type] => 1
[patent_app_number] => 9/487599
[patent_app_country] => US
[patent_app_date] => 2000-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 50
[patent_figures_cnt] => 118
[patent_no_of_words] => 16561
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 320
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/238/06238961.pdf
[firstpage_image] =>[orig_patent_app_number] => 487599
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/487599 | Semiconductor integrated circuit device and process for manufacturing the same | Jan 18, 2000 | Issued |