Search

Barbara J Bullock

Examiner (ID: 9881)

Most Active Art Unit
2901
Art Unit(s)
2900, 2912, 2901, 2902
Total Applications
4468
Issued Applications
4372
Pending Applications
0
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1306375 [patent_doc_number] => 06613105 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-02 [patent_title] => 'System for filling openings in semiconductor products' [patent_app_type] => B1 [patent_app_number] => 09/471119 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 4242 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/613/06613105.pdf [firstpage_image] =>[orig_patent_app_number] => 09471119 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/471119
System for filling openings in semiconductor products Dec 22, 1999 Issued
Array ( [id] => 4312768 [patent_doc_number] => 06242331 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Method to reduce device contact resistance using a hydrogen peroxide treatment' [patent_app_type] => 1 [patent_app_number] => 9/467129 [patent_app_country] => US [patent_app_date] => 1999-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2450 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/242/06242331.pdf [firstpage_image] =>[orig_patent_app_number] => 467129 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/467129
Method to reduce device contact resistance using a hydrogen peroxide treatment Dec 19, 1999 Issued
Array ( [id] => 6269498 [patent_doc_number] => 20020105033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-08 [patent_title] => 'THIN FILM TRANSISTOR HAVING LIGHTLY AND HEAVILY DOPED SOURCE/DRAIN REGIONS AND ITS MANUFACTURE' [patent_app_type] => new [patent_app_number] => 09/468489 [patent_app_country] => US [patent_app_date] => 1999-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12124 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20020105033.pdf [firstpage_image] =>[orig_patent_app_number] => 09468489 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/468489
THIN FILM TRANSISTOR HAVING LIGHTLY AND HEAVILY DOPED SOURCE/DRAIN REGIONS AND ITS MANUFACTURE Dec 19, 1999 Abandoned
Array ( [id] => 7636641 [patent_doc_number] => 06380014 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Manufacture method of semiconductor device with suppressed impurity diffusion from gate electrode' [patent_app_type] => B1 [patent_app_number] => 09/461005 [patent_app_country] => US [patent_app_date] => 1999-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 44 [patent_no_of_words] => 7285 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/380/06380014.pdf [firstpage_image] =>[orig_patent_app_number] => 09461005 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/461005
Manufacture method of semiconductor device with suppressed impurity diffusion from gate electrode Dec 14, 1999 Issued
Array ( [id] => 4168658 [patent_doc_number] => 06140155 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Method of manufacturing semiconductor device using dry photoresist film' [patent_app_type] => 1 [patent_app_number] => 9/459019 [patent_app_country] => US [patent_app_date] => 1999-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 6018 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/140/06140155.pdf [firstpage_image] =>[orig_patent_app_number] => 459019 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/459019
Method of manufacturing semiconductor device using dry photoresist film Dec 9, 1999 Issued
Array ( [id] => 1486820 [patent_doc_number] => 06365970 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Bond pad structure and its method of fabricating' [patent_app_type] => B1 [patent_app_number] => 09/458778 [patent_app_country] => US [patent_app_date] => 1999-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3391 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/365/06365970.pdf [firstpage_image] =>[orig_patent_app_number] => 09458778 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/458778
Bond pad structure and its method of fabricating Dec 9, 1999 Issued
Array ( [id] => 4246436 [patent_doc_number] => 06136692 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Method for forming metal plug electrode in semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/455058 [patent_app_country] => US [patent_app_date] => 1999-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2863 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/136/06136692.pdf [firstpage_image] =>[orig_patent_app_number] => 455058 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/455058
Method for forming metal plug electrode in semiconductor device Dec 5, 1999 Issued
Array ( [id] => 4325268 [patent_doc_number] => 06329281 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Methods for fabricating a multilevel interconnection for an integrated circuit device utilizing a selective overlayer' [patent_app_type] => 1 [patent_app_number] => 9/454909 [patent_app_country] => US [patent_app_date] => 1999-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 6846 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329281.pdf [firstpage_image] =>[orig_patent_app_number] => 454909 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/454909
Methods for fabricating a multilevel interconnection for an integrated circuit device utilizing a selective overlayer Dec 2, 1999 Issued
Array ( [id] => 4376858 [patent_doc_number] => 06288450 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Wiring structure for semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/449908 [patent_app_country] => US [patent_app_date] => 1999-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4304 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288450.pdf [firstpage_image] =>[orig_patent_app_number] => 449908 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/449908
Wiring structure for semiconductor device Dec 1, 1999 Issued
09/451221 SEMICONDUCTOR DEVICE Nov 28, 1999 Abandoned
Array ( [id] => 1461538 [patent_doc_number] => 06392299 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Integrated circuit and associated fabrication process' [patent_app_type] => B1 [patent_app_number] => 09/449309 [patent_app_country] => US [patent_app_date] => 1999-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3766 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/392/06392299.pdf [firstpage_image] =>[orig_patent_app_number] => 09449309 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/449309
Integrated circuit and associated fabrication process Nov 23, 1999 Issued
Array ( [id] => 4377899 [patent_doc_number] => 06303459 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Integration process for Al pad' [patent_app_type] => 1 [patent_app_number] => 9/439359 [patent_app_country] => US [patent_app_date] => 1999-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 3767 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/303/06303459.pdf [firstpage_image] =>[orig_patent_app_number] => 439359 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/439359
Integration process for Al pad Nov 14, 1999 Issued
Array ( [id] => 4326197 [patent_doc_number] => 06331732 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Via structure in an integrated circuit utilizing a high conductivity metal interconnect and a method for manufacturing same' [patent_app_type] => 1 [patent_app_number] => 9/439948 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 1934 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/331/06331732.pdf [firstpage_image] =>[orig_patent_app_number] => 439948 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/439948
Via structure in an integrated circuit utilizing a high conductivity metal interconnect and a method for manufacturing same Nov 11, 1999 Issued
Array ( [id] => 4354349 [patent_doc_number] => 06218287 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Method of fabricating a semiconductor structure' [patent_app_type] => 1 [patent_app_number] => 9/435839 [patent_app_country] => US [patent_app_date] => 1999-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2056 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218287.pdf [firstpage_image] =>[orig_patent_app_number] => 435839 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/435839
Method of fabricating a semiconductor structure Nov 7, 1999 Issued
Array ( [id] => 4124866 [patent_doc_number] => 06127228 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Method of forming buried bit line' [patent_app_type] => 1 [patent_app_number] => 9/435399 [patent_app_country] => US [patent_app_date] => 1999-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 2929 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127228.pdf [firstpage_image] =>[orig_patent_app_number] => 435399 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/435399
Method of forming buried bit line Nov 5, 1999 Issued
Array ( [id] => 4258409 [patent_doc_number] => 06204134 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Method for fabricating a self aligned contact plug' [patent_app_type] => 1 [patent_app_number] => 9/431239 [patent_app_country] => US [patent_app_date] => 1999-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1852 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204134.pdf [firstpage_image] =>[orig_patent_app_number] => 431239 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/431239
Method for fabricating a self aligned contact plug Oct 31, 1999 Issued
Array ( [id] => 4286566 [patent_doc_number] => 06211059 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Method of manufacturing semiconductor device having contacts with different depths' [patent_app_type] => 1 [patent_app_number] => 9/429479 [patent_app_country] => US [patent_app_date] => 1999-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3483 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/211/06211059.pdf [firstpage_image] =>[orig_patent_app_number] => 429479 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/429479
Method of manufacturing semiconductor device having contacts with different depths Oct 28, 1999 Issued
Array ( [id] => 4353498 [patent_doc_number] => 06218227 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Method to generate a MONOS type flash cell using polycrystalline silicon as an ONO top layer' [patent_app_type] => 1 [patent_app_number] => 9/426239 [patent_app_country] => US [patent_app_date] => 1999-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2062 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218227.pdf [firstpage_image] =>[orig_patent_app_number] => 426239 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/426239
Method to generate a MONOS type flash cell using polycrystalline silicon as an ONO top layer Oct 24, 1999 Issued
Array ( [id] => 4287203 [patent_doc_number] => 06268287 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Polymerless metal hard mask etching' [patent_app_type] => 1 [patent_app_number] => 9/419109 [patent_app_country] => US [patent_app_date] => 1999-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1872 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268287.pdf [firstpage_image] =>[orig_patent_app_number] => 419109 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/419109
Polymerless metal hard mask etching Oct 14, 1999 Issued
Array ( [id] => 4245765 [patent_doc_number] => 06136649 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Method for removing anti-reflective coating layer using plasma etch process after contact CMP' [patent_app_type] => 1 [patent_app_number] => 9/416389 [patent_app_country] => US [patent_app_date] => 1999-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 5088 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/136/06136649.pdf [firstpage_image] =>[orig_patent_app_number] => 416389 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/416389
Method for removing anti-reflective coating layer using plasma etch process after contact CMP Oct 11, 1999 Issued
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