Search

Barbara J Bullock

Examiner (ID: 9881)

Most Active Art Unit
2901
Art Unit(s)
2900, 2912, 2901, 2902
Total Applications
4468
Issued Applications
4372
Pending Applications
0
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
09/415649 METHOD AND APPARATUS FOR LINING CONTACT, VIA AND TRENCH LAYERS WITH HIGH-DENSITY IONIZED METAL PLASMA (IMP) TITANIUM AND CVD TITANIUM NITRIDE LAYERS Oct 11, 1999 Abandoned
Array ( [id] => 4131596 [patent_doc_number] => 06146984 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Method and structure for uniform height solder bumps on a semiconductor wafer' [patent_app_type] => 1 [patent_app_number] => 9/415319 [patent_app_country] => US [patent_app_date] => 1999-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3700 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/146/06146984.pdf [firstpage_image] =>[orig_patent_app_number] => 415319 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/415319
Method and structure for uniform height solder bumps on a semiconductor wafer Oct 7, 1999 Issued
Array ( [id] => 1523582 [patent_doc_number] => 06352871 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Probe grid for integrated circuit excitation' [patent_app_type] => B1 [patent_app_number] => 09/409089 [patent_app_country] => US [patent_app_date] => 1999-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3051 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/352/06352871.pdf [firstpage_image] =>[orig_patent_app_number] => 09409089 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/409089
Probe grid for integrated circuit excitation Sep 29, 1999 Issued
09/407209 INTEGRATED CIRCUITS WITH BARRIER LAYERS AND METHODS OF FABRICATING SAME Sep 27, 1999 Abandoned
Array ( [id] => 4181916 [patent_doc_number] => 06150199 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Method for fabrication of programmable interconnect structure' [patent_app_type] => 1 [patent_app_number] => 9/405979 [patent_app_country] => US [patent_app_date] => 1999-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5702 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150199.pdf [firstpage_image] =>[orig_patent_app_number] => 405979 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/405979
Method for fabrication of programmable interconnect structure Sep 26, 1999 Issued
Array ( [id] => 4348538 [patent_doc_number] => 06214723 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/391388 [patent_app_country] => US [patent_app_date] => 1999-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 4757 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/214/06214723.pdf [firstpage_image] =>[orig_patent_app_number] => 391388 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/391388
Method of manufacturing a semiconductor device Sep 7, 1999 Issued
Array ( [id] => 1463682 [patent_doc_number] => 06351016 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Technology for high performance buried contact and tungsten polycide gate integration' [patent_app_type] => B1 [patent_app_number] => 09/389630 [patent_app_country] => US [patent_app_date] => 1999-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 2803 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351016.pdf [firstpage_image] =>[orig_patent_app_number] => 09389630 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/389630
Technology for high performance buried contact and tungsten polycide gate integration Sep 2, 1999 Issued
Array ( [id] => 4292675 [patent_doc_number] => 06180508 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Methods of fabricating buried digit lines and semiconductor devices including same' [patent_app_type] => 1 [patent_app_number] => 9/388769 [patent_app_country] => US [patent_app_date] => 1999-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 4863 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/180/06180508.pdf [firstpage_image] =>[orig_patent_app_number] => 388769 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/388769
Methods of fabricating buried digit lines and semiconductor devices including same Sep 1, 1999 Issued
Array ( [id] => 4290113 [patent_doc_number] => 06235620 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Process for manufacturing semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 9/382329 [patent_app_country] => US [patent_app_date] => 1999-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 59 [patent_no_of_words] => 19579 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/235/06235620.pdf [firstpage_image] =>[orig_patent_app_number] => 382329 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/382329
Process for manufacturing semiconductor integrated circuit device Aug 23, 1999 Issued
Array ( [id] => 4290138 [patent_doc_number] => 06235622 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Method and apparatus for isolating a conductive region from a substrate during manufacture of an integrated circuit and connected to the substrate after manufacture' [patent_app_type] => 1 [patent_app_number] => 9/382219 [patent_app_country] => US [patent_app_date] => 1999-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3465 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/235/06235622.pdf [firstpage_image] =>[orig_patent_app_number] => 382219 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/382219
Method and apparatus for isolating a conductive region from a substrate during manufacture of an integrated circuit and connected to the substrate after manufacture Aug 23, 1999 Issued
Array ( [id] => 4070490 [patent_doc_number] => 06069032 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Salicide process' [patent_app_type] => 1 [patent_app_number] => 9/375619 [patent_app_country] => US [patent_app_date] => 1999-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 1807 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/069/06069032.pdf [firstpage_image] =>[orig_patent_app_number] => 375619 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/375619
Salicide process Aug 16, 1999 Issued
Array ( [id] => 4335928 [patent_doc_number] => 06333205 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'CMOS imager with selectively silicided gates' [patent_app_type] => 1 [patent_app_number] => 9/374990 [patent_app_country] => US [patent_app_date] => 1999-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 7514 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/333/06333205.pdf [firstpage_image] =>[orig_patent_app_number] => 374990 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/374990
CMOS imager with selectively silicided gates Aug 15, 1999 Issued
Array ( [id] => 4182677 [patent_doc_number] => 06150254 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Method for wiring of a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/373283 [patent_app_country] => US [patent_app_date] => 1999-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 4512 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150254.pdf [firstpage_image] =>[orig_patent_app_number] => 373283 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/373283
Method for wiring of a semiconductor device Aug 11, 1999 Issued
Array ( [id] => 4411023 [patent_doc_number] => 06271592 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Sputter deposited barrier layers' [patent_app_type] => 1 [patent_app_number] => 9/370088 [patent_app_country] => US [patent_app_date] => 1999-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 7101 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271592.pdf [firstpage_image] =>[orig_patent_app_number] => 370088 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/370088
Sputter deposited barrier layers Aug 5, 1999 Issued
Array ( [id] => 4294619 [patent_doc_number] => 06184132 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Integrated cobalt silicide process for semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 9/365859 [patent_app_country] => US [patent_app_date] => 1999-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3222 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184132.pdf [firstpage_image] =>[orig_patent_app_number] => 365859 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/365859
Integrated cobalt silicide process for semiconductor devices Aug 2, 1999 Issued
Array ( [id] => 4312886 [patent_doc_number] => 06242340 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Method for forming an interconnection in a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/362898 [patent_app_country] => US [patent_app_date] => 1999-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2654 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/242/06242340.pdf [firstpage_image] =>[orig_patent_app_number] => 362898 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/362898
Method for forming an interconnection in a semiconductor device Jul 28, 1999 Issued
Array ( [id] => 4302307 [patent_doc_number] => 06187617 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Semiconductor structure having heterogeneous silicide regions and method for forming same' [patent_app_type] => 1 [patent_app_number] => 9/363558 [patent_app_country] => US [patent_app_date] => 1999-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4561 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/187/06187617.pdf [firstpage_image] =>[orig_patent_app_number] => 363558 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/363558
Semiconductor structure having heterogeneous silicide regions and method for forming same Jul 28, 1999 Issued
Array ( [id] => 4304239 [patent_doc_number] => 06326299 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Method for manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/361989 [patent_app_country] => US [patent_app_date] => 1999-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 24 [patent_no_of_words] => 15187 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326299.pdf [firstpage_image] =>[orig_patent_app_number] => 361989 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/361989
Method for manufacturing a semiconductor device Jul 27, 1999 Issued
Array ( [id] => 4237492 [patent_doc_number] => 06090698 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Fabrication method for an insulation structure having a low dielectric constant' [patent_app_type] => 1 [patent_app_number] => 9/359518 [patent_app_country] => US [patent_app_date] => 1999-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2590 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/090/06090698.pdf [firstpage_image] =>[orig_patent_app_number] => 359518 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/359518
Fabrication method for an insulation structure having a low dielectric constant Jul 22, 1999 Issued
Array ( [id] => 4348507 [patent_doc_number] => 06214721 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Method and structure for suppressing light reflections during photolithography exposure steps in processing integrated circuit structures' [patent_app_type] => 1 [patent_app_number] => 9/358519 [patent_app_country] => US [patent_app_date] => 1999-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1485 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/214/06214721.pdf [firstpage_image] =>[orig_patent_app_number] => 358519 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/358519
Method and structure for suppressing light reflections during photolithography exposure steps in processing integrated circuit structures Jul 21, 1999 Issued
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