Search

Barbara J Bullock

Examiner (ID: 9881)

Most Active Art Unit
2901
Art Unit(s)
2900, 2912, 2901, 2902
Total Applications
4468
Issued Applications
4372
Pending Applications
0
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4206956 [patent_doc_number] => 06027995 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Method for fabricating an interconnect structure with hard mask and low dielectric constant materials' [patent_app_type] => 1 [patent_app_number] => 9/135618 [patent_app_country] => US [patent_app_date] => 1998-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2973 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/027/06027995.pdf [firstpage_image] =>[orig_patent_app_number] => 135618 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/135618
Method for fabricating an interconnect structure with hard mask and low dielectric constant materials Aug 17, 1998 Issued
Array ( [id] => 4084316 [patent_doc_number] => 06162715 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Method of forming gate electrode connection structure by in situ chemical vapor deposition of tungsten and tungsten nitride' [patent_app_type] => 1 [patent_app_number] => 9/114839 [patent_app_country] => US [patent_app_date] => 1998-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 9722 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/162/06162715.pdf [firstpage_image] =>[orig_patent_app_number] => 114839 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/114839
Method of forming gate electrode connection structure by in situ chemical vapor deposition of tungsten and tungsten nitride Jul 13, 1998 Issued
Array ( [id] => 1336485 [patent_doc_number] => 06593233 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => B1 [patent_app_number] => 09/093819 [patent_app_country] => US [patent_app_date] => 1998-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 30 [patent_no_of_words] => 6011 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/593/06593233.pdf [firstpage_image] =>[orig_patent_app_number] => 09093819 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/093819
Semiconductor device and method for manufacturing the same Jun 8, 1998 Issued
Array ( [id] => 4131094 [patent_doc_number] => 06121089 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Methods of forming power semiconductor devices having merged split-well body regions therein' [patent_app_type] => 1 [patent_app_number] => 9/092334 [patent_app_country] => US [patent_app_date] => 1998-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 7154 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121089.pdf [firstpage_image] =>[orig_patent_app_number] => 092334 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/092334
Methods of forming power semiconductor devices having merged split-well body regions therein Jun 4, 1998 Issued
Array ( [id] => 4107467 [patent_doc_number] => 06057198 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Semiconductor processing method of forming a buried contact' [patent_app_type] => 1 [patent_app_number] => 9/087133 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 2247 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057198.pdf [firstpage_image] =>[orig_patent_app_number] => 087133 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/087133
Semiconductor processing method of forming a buried contact May 28, 1998 Issued
Array ( [id] => 3943988 [patent_doc_number] => 05976963 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Self-aligned metallurgy' [patent_app_type] => 1 [patent_app_number] => 9/084518 [patent_app_country] => US [patent_app_date] => 1998-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6254 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/976/05976963.pdf [firstpage_image] =>[orig_patent_app_number] => 084518 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/084518
Self-aligned metallurgy May 25, 1998 Issued
Array ( [id] => 3944646 [patent_doc_number] => 05998294 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Method for forming improved electrical contacts on non-planar structures' [patent_app_type] => 1 [patent_app_number] => 9/069388 [patent_app_country] => US [patent_app_date] => 1998-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 1975 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/998/05998294.pdf [firstpage_image] =>[orig_patent_app_number] => 069388 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/069388
Method for forming improved electrical contacts on non-planar structures Apr 28, 1998 Issued
Array ( [id] => 4085115 [patent_doc_number] => 06025264 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Fabricating method of a barrier layer' [patent_app_type] => 1 [patent_app_number] => 9/052608 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2403 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/025/06025264.pdf [firstpage_image] =>[orig_patent_app_number] => 052608 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/052608
Fabricating method of a barrier layer Mar 30, 1998 Issued
Array ( [id] => 4031428 [patent_doc_number] => 05907781 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Process for fabricating an integrated circuit with a self-aligned contact' [patent_app_type] => 1 [patent_app_number] => 9/049517 [patent_app_country] => US [patent_app_date] => 1998-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2548 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907781.pdf [firstpage_image] =>[orig_patent_app_number] => 049517 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/049517
Process for fabricating an integrated circuit with a self-aligned contact Mar 26, 1998 Issued
Array ( [id] => 3937934 [patent_doc_number] => 05981382 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'PVD deposition process for CVD aluminum liner processing' [patent_app_type] => 1 [patent_app_number] => 9/042199 [patent_app_country] => US [patent_app_date] => 1998-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3202 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/981/05981382.pdf [firstpage_image] =>[orig_patent_app_number] => 042199 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/042199
PVD deposition process for CVD aluminum liner processing Mar 12, 1998 Issued
Array ( [id] => 3953447 [patent_doc_number] => 05998871 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Metal plug electrode in semiconductor device and method for forming the same' [patent_app_type] => 1 [patent_app_number] => 9/027346 [patent_app_country] => US [patent_app_date] => 1998-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 2861 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/998/05998871.pdf [firstpage_image] =>[orig_patent_app_number] => 027346 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/027346
Metal plug electrode in semiconductor device and method for forming the same Feb 19, 1998 Issued
Array ( [id] => 3942067 [patent_doc_number] => 05989996 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/022009 [patent_app_country] => US [patent_app_date] => 1998-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 4103 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/989/05989996.pdf [firstpage_image] =>[orig_patent_app_number] => 022009 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/022009
Method for manufacturing semiconductor device Feb 10, 1998 Issued
Array ( [id] => 4080630 [patent_doc_number] => 06054341 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Method of manufacturing charge-coupled device having different light-receiving region and charge-isolating layer structures' [patent_app_type] => 1 [patent_app_number] => 9/017800 [patent_app_country] => US [patent_app_date] => 1998-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 2623 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/054/06054341.pdf [firstpage_image] =>[orig_patent_app_number] => 017800 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/017800
Method of manufacturing charge-coupled device having different light-receiving region and charge-isolating layer structures Feb 2, 1998 Issued
Array ( [id] => 4236001 [patent_doc_number] => 06143645 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Reduced temperature contact/via filling' [patent_app_type] => 1 [patent_app_number] => 9/016118 [patent_app_country] => US [patent_app_date] => 1998-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3274 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/143/06143645.pdf [firstpage_image] =>[orig_patent_app_number] => 016118 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/016118
Reduced temperature contact/via filling Jan 29, 1998 Issued
Array ( [id] => 4420584 [patent_doc_number] => 06225213 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Manufacturing method for contact hole' [patent_app_type] => 1 [patent_app_number] => 9/010578 [patent_app_country] => US [patent_app_date] => 1998-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2200 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225213.pdf [firstpage_image] =>[orig_patent_app_number] => 010578 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/010578
Manufacturing method for contact hole Jan 21, 1998 Issued
Array ( [id] => 1209395 [patent_doc_number] => 06713384 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'Contact integration method' [patent_app_type] => B1 [patent_app_number] => 09/007949 [patent_app_country] => US [patent_app_date] => 1998-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5063 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/713/06713384.pdf [firstpage_image] =>[orig_patent_app_number] => 09007949 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/007949
Contact integration method Jan 15, 1998 Issued
09/006309 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Jan 12, 1998 Issued
Array ( [id] => 4057187 [patent_doc_number] => 05895244 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Process to fabricate ultra-short channel nMOSFETs with self-aligned silicide contact' [patent_app_type] => 1 [patent_app_number] => 9/004449 [patent_app_country] => US [patent_app_date] => 1998-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2224 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/895/05895244.pdf [firstpage_image] =>[orig_patent_app_number] => 004449 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/004449
Process to fabricate ultra-short channel nMOSFETs with self-aligned silicide contact Jan 7, 1998 Issued
Array ( [id] => 4037723 [patent_doc_number] => 05994725 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'MOSFET having Schottky gate and bipolar device' [patent_app_type] => 1 [patent_app_number] => 9/003438 [patent_app_country] => US [patent_app_date] => 1998-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 39 [patent_no_of_words] => 7250 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/994/05994725.pdf [firstpage_image] =>[orig_patent_app_number] => 003438 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/003438
MOSFET having Schottky gate and bipolar device Jan 5, 1998 Issued
Array ( [id] => 3945577 [patent_doc_number] => 05953625 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Air voids underneath metal lines to reduce parasitic capacitance' [patent_app_type] => 1 [patent_app_number] => 8/990270 [patent_app_country] => US [patent_app_date] => 1997-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 15 [patent_no_of_words] => 2757 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/953/05953625.pdf [firstpage_image] =>[orig_patent_app_number] => 990270 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/990270
Air voids underneath metal lines to reduce parasitic capacitance Dec 14, 1997 Issued
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