Application number | Title of the application | Filing Date | Status |
---|
Array
(
[id] => 4007005
[patent_doc_number] => 05888887
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-30
[patent_title] => 'Trenchless buried contact process technology'
[patent_app_type] => 1
[patent_app_number] => 8/990697
[patent_app_country] => US
[patent_app_date] => 1997-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 2679
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/888/05888887.pdf
[firstpage_image] =>[orig_patent_app_number] => 990697
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/990697 | Trenchless buried contact process technology | Dec 14, 1997 | Issued |
Array
(
[id] => 4233285
[patent_doc_number] => 06117761
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-12
[patent_title] => 'Self-aligned silicide strap connection of polysilicon layers'
[patent_app_type] => 1
[patent_app_number] => 8/990346
[patent_app_country] => US
[patent_app_date] => 1997-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 4033
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/117/06117761.pdf
[firstpage_image] =>[orig_patent_app_number] => 990346
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/990346 | Self-aligned silicide strap connection of polysilicon layers | Dec 14, 1997 | Issued |
Array
(
[id] => 4358087
[patent_doc_number] => 06191033
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-20
[patent_title] => 'Method of fabricating an integrated circuit with improved contact barrier'
[patent_app_type] => 1
[patent_app_number] => 8/980468
[patent_app_country] => US
[patent_app_date] => 1997-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 18
[patent_no_of_words] => 6195
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/191/06191033.pdf
[firstpage_image] =>[orig_patent_app_number] => 980468
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/980468 | Method of fabricating an integrated circuit with improved contact barrier | Nov 27, 1997 | Issued |
Array
(
[id] => 4130426
[patent_doc_number] => 06033980
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-07
[patent_title] => 'Method of forming submicron contacts and vias in an integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/978382
[patent_app_country] => US
[patent_app_date] => 1997-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 17
[patent_no_of_words] => 5273
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/033/06033980.pdf
[firstpage_image] =>[orig_patent_app_number] => 978382
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/978382 | Method of forming submicron contacts and vias in an integrated circuit | Nov 24, 1997 | Issued |
Array
(
[id] => 4007121
[patent_doc_number] => 05888895
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-30
[patent_title] => 'Method for making titanium poly-silicide CMOS circuit contacts'
[patent_app_type] => 1
[patent_app_number] => 8/978093
[patent_app_country] => US
[patent_app_date] => 1997-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 16
[patent_no_of_words] => 1698
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/888/05888895.pdf
[firstpage_image] =>[orig_patent_app_number] => 978093
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/978093 | Method for making titanium poly-silicide CMOS circuit contacts | Nov 24, 1997 | Issued |
Array
(
[id] => 4007105
[patent_doc_number] => 05888894
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-30
[patent_title] => 'Method for reducing stray conductive material near vertical surfaces in semiconductor manufacturing processes'
[patent_app_type] => 1
[patent_app_number] => 8/965912
[patent_app_country] => US
[patent_app_date] => 1997-11-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 12
[patent_no_of_words] => 2378
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/888/05888894.pdf
[firstpage_image] =>[orig_patent_app_number] => 965912
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/965912 | Method for reducing stray conductive material near vertical surfaces in semiconductor manufacturing processes | Nov 6, 1997 | Issued |
Array
(
[id] => 4009467
[patent_doc_number] => 05920791
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-06
[patent_title] => 'Method of manufacturing intermetal dielectrics for sub-half-micron semiconductor devices'
[patent_app_type] => 1
[patent_app_number] => 8/965318
[patent_app_country] => US
[patent_app_date] => 1997-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 1441
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/920/05920791.pdf
[firstpage_image] =>[orig_patent_app_number] => 965318
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/965318 | Method of manufacturing intermetal dielectrics for sub-half-micron semiconductor devices | Nov 5, 1997 | Issued |
Array
(
[id] => 3976617
[patent_doc_number] => 05937319
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-10
[patent_title] => 'Method of making a metal oxide semiconductor (MOS) transistor polysilicon gate with a size beyond photolithography limitation by using polysilicidation and selective etching'
[patent_app_type] => 1
[patent_app_number] => 8/961828
[patent_app_country] => US
[patent_app_date] => 1997-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 3104
[patent_no_of_claims] => 58
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/937/05937319.pdf
[firstpage_image] =>[orig_patent_app_number] => 961828
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/961828 | Method of making a metal oxide semiconductor (MOS) transistor polysilicon gate with a size beyond photolithography limitation by using polysilicidation and selective etching | Oct 30, 1997 | Issued |
Array
(
[id] => 4002881
[patent_doc_number] => 06004855
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-21
[patent_title] => 'Process for producing a high performance bipolar structure'
[patent_app_type] => 1
[patent_app_number] => 8/967322
[patent_app_country] => US
[patent_app_date] => 1997-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 10
[patent_no_of_words] => 5261
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 566
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/004/06004855.pdf
[firstpage_image] =>[orig_patent_app_number] => 967322
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/967322 | Process for producing a high performance bipolar structure | Oct 28, 1997 | Issued |
Array
(
[id] => 3884782
[patent_doc_number] => 05776830
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-07
[patent_title] => 'Process for fabricating connection structures'
[patent_app_type] => 1
[patent_app_number] => 8/947704
[patent_app_country] => US
[patent_app_date] => 1997-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 4520
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/776/05776830.pdf
[firstpage_image] =>[orig_patent_app_number] => 947704
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/947704 | Process for fabricating connection structures | Oct 8, 1997 | Issued |
Array
(
[id] => 4312966
[patent_doc_number] => 06242346
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-05
[patent_title] => 'Metallization for uncovered contacts and vias'
[patent_app_type] => 1
[patent_app_number] => 8/948369
[patent_app_country] => US
[patent_app_date] => 1997-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 3610
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/242/06242346.pdf
[firstpage_image] =>[orig_patent_app_number] => 948369
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/948369 | Metallization for uncovered contacts and vias | Oct 8, 1997 | Issued |
Array
(
[id] => 3926409
[patent_doc_number] => 05877084
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-02
[patent_title] => 'Method for fabricating high aspect ratio low resistivity lines/vias by surface reaction'
[patent_app_type] => 1
[patent_app_number] => 8/941062
[patent_app_country] => US
[patent_app_date] => 1997-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 20
[patent_no_of_words] => 7322
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/877/05877084.pdf
[firstpage_image] =>[orig_patent_app_number] => 941062
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/941062 | Method for fabricating high aspect ratio low resistivity lines/vias by surface reaction | Sep 29, 1997 | Issued |
Array
(
[id] => 3993794
[patent_doc_number] => 05985724
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-16
[patent_title] => 'Method for forming asymmetrical p-channel transistor having nitrided oxide patterned to selectively form a sidewall spacer'
[patent_app_type] => 1
[patent_app_number] => 8/937069
[patent_app_country] => US
[patent_app_date] => 1997-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 33
[patent_no_of_words] => 9163
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 263
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/985/05985724.pdf
[firstpage_image] =>[orig_patent_app_number] => 937069
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/937069 | Method for forming asymmetrical p-channel transistor having nitrided oxide patterned to selectively form a sidewall spacer | Sep 23, 1997 | Issued |
Array
(
[id] => 3994290
[patent_doc_number] => 05985758
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-16
[patent_title] => 'Method for forming metal lines of semiconductor devices'
[patent_app_type] => 1
[patent_app_number] => 8/934766
[patent_app_country] => US
[patent_app_date] => 1997-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 1814
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/985/05985758.pdf
[firstpage_image] =>[orig_patent_app_number] => 934766
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/934766 | Method for forming metal lines of semiconductor devices | Sep 21, 1997 | Issued |
Array
(
[id] => 3950683
[patent_doc_number] => 05899735
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-04
[patent_title] => 'Method for making low-resistance contacts between polysilicon and metal silicide on semiconductor integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 8/933960
[patent_app_country] => US
[patent_app_date] => 1997-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 3356
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 242
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/899/05899735.pdf
[firstpage_image] =>[orig_patent_app_number] => 933960
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/933960 | Method for making low-resistance contacts between polysilicon and metal silicide on semiconductor integrated circuits | Sep 18, 1997 | Issued |
Array
(
[id] => 4218993
[patent_doc_number] => 06040225
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-21
[patent_title] => 'Method of fabricating polysilicon based resistors in Si-Ge heterojunction devices'
[patent_app_type] => 1
[patent_app_number] => 8/920639
[patent_app_country] => US
[patent_app_date] => 1997-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 2489
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 214
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/040/06040225.pdf
[firstpage_image] =>[orig_patent_app_number] => 920639
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/920639 | Method of fabricating polysilicon based resistors in Si-Ge heterojunction devices | Aug 28, 1997 | Issued |
Array
(
[id] => 3760193
[patent_doc_number] => 05851890
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-22
[patent_title] => 'Process for forming integrated circuit structure with metal silicide contacts using notched sidewall spacer on gate electrode'
[patent_app_type] => 1
[patent_app_number] => 8/919394
[patent_app_country] => US
[patent_app_date] => 1997-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 3871
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 291
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/851/05851890.pdf
[firstpage_image] =>[orig_patent_app_number] => 919394
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/919394 | Process for forming integrated circuit structure with metal silicide contacts using notched sidewall spacer on gate electrode | Aug 27, 1997 | Issued |
Array
(
[id] => 3991323
[patent_doc_number] => 05891799
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-06
[patent_title] => 'Method for making stacked and borderless via structures for multilevel metal interconnections on semiconductor substrates'
[patent_app_type] => 1
[patent_app_number] => 8/912326
[patent_app_country] => US
[patent_app_date] => 1997-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 20
[patent_no_of_words] => 4110
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 287
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/891/05891799.pdf
[firstpage_image] =>[orig_patent_app_number] => 912326
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/912326 | Method for making stacked and borderless via structures for multilevel metal interconnections on semiconductor substrates | Aug 17, 1997 | Issued |
Array
(
[id] => 4100119
[patent_doc_number] => 06066549
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-23
[patent_title] => 'Semiconductor processing method of forming a conductive gate line and semiconductor processing method of making ohmic contact between a transistor gate line and a substrate diffusion region'
[patent_app_type] => 1
[patent_app_number] => 8/914307
[patent_app_country] => US
[patent_app_date] => 1997-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 18
[patent_no_of_words] => 2323
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/066/06066549.pdf
[firstpage_image] =>[orig_patent_app_number] => 914307
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/914307 | Semiconductor processing method of forming a conductive gate line and semiconductor processing method of making ohmic contact between a transistor gate line and a substrate diffusion region | Aug 17, 1997 | Issued |
Array
(
[id] => 4059053
[patent_doc_number] => 05913139
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-15
[patent_title] => 'Method of manufacturing a semiconductor device with local interconnect of metal silicide'
[patent_app_type] => 1
[patent_app_number] => 8/907637
[patent_app_country] => US
[patent_app_date] => 1997-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 18
[patent_no_of_words] => 7031
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/913/05913139.pdf
[firstpage_image] =>[orig_patent_app_number] => 907637
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/907637 | Method of manufacturing a semiconductor device with local interconnect of metal silicide | Aug 7, 1997 | Issued |