Search

Barbara J Bullock

Examiner (ID: 9881)

Most Active Art Unit
2901
Art Unit(s)
2900, 2912, 2901, 2902
Total Applications
4468
Issued Applications
4372
Pending Applications
0
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3982605 [patent_doc_number] => 05861322 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-19 [patent_title] => 'Process for manufacturing an interconnection substrate to connect a chip onto a reception substrate' [patent_app_type] => 1 [patent_app_number] => 8/658684 [patent_app_country] => US [patent_app_date] => 1996-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 3170 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/861/05861322.pdf [firstpage_image] =>[orig_patent_app_number] => 658684 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/658684
Process for manufacturing an interconnection substrate to connect a chip onto a reception substrate Jun 4, 1996 Issued
Array ( [id] => 3894691 [patent_doc_number] => 05750438 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Method for fabricating a local interconnection structure' [patent_app_type] => 1 [patent_app_number] => 8/658032 [patent_app_country] => US [patent_app_date] => 1996-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2139 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/750/05750438.pdf [firstpage_image] =>[orig_patent_app_number] => 658032 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/658032
Method for fabricating a local interconnection structure Jun 3, 1996 Issued
Array ( [id] => 4107708 [patent_doc_number] => 06057215 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Process for forming a refractory metal silicide film having a uniform thickness' [patent_app_type] => 1 [patent_app_number] => 8/660186 [patent_app_country] => US [patent_app_date] => 1996-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4065 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057215.pdf [firstpage_image] =>[orig_patent_app_number] => 660186 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/660186
Process for forming a refractory metal silicide film having a uniform thickness May 30, 1996 Issued
08/654755 PROCESS FOR FABRICATING CONNECTION STRUCTURES May 28, 1996 Abandoned
Array ( [id] => 3681981 [patent_doc_number] => 05633200 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-27 [patent_title] => 'Process for manufacturing a large grain tungsten nitride film and process for manufacturing a lightly nitrided titanium salicide diffusion barrier with a large grain tungsten nitride cover layer' [patent_app_type] => 1 [patent_app_number] => 8/653428 [patent_app_country] => US [patent_app_date] => 1996-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 5052 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/633/05633200.pdf [firstpage_image] =>[orig_patent_app_number] => 653428 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/653428
Process for manufacturing a large grain tungsten nitride film and process for manufacturing a lightly nitrided titanium salicide diffusion barrier with a large grain tungsten nitride cover layer May 23, 1996 Issued
08/657056 METHOD OF PREVENTING ALUMINUM SPUTTERING DURING OXIDE VIA ETCHING May 23, 1996 Abandoned
08/650356 ALCU METAL DEPOSITION FOR ROBUST RC VIA PERFORMANCE May 19, 1996 Abandoned
Array ( [id] => 3730108 [patent_doc_number] => 05693561 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Method of integrated circuit fabrication including a step of depositing tungsten' [patent_app_type] => 1 [patent_app_number] => 8/645852 [patent_app_country] => US [patent_app_date] => 1996-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1561 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/693/05693561.pdf [firstpage_image] =>[orig_patent_app_number] => 645852 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/645852
Method of integrated circuit fabrication including a step of depositing tungsten May 13, 1996 Issued
Array ( [id] => 3757094 [patent_doc_number] => 05721157 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-24 [patent_title] => 'Method for manufacturing a semiconductor device having interconnection layers' [patent_app_type] => 1 [patent_app_number] => 8/642858 [patent_app_country] => US [patent_app_date] => 1996-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 18 [patent_no_of_words] => 4046 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/721/05721157.pdf [firstpage_image] =>[orig_patent_app_number] => 642858 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/642858
Method for manufacturing a semiconductor device having interconnection layers May 5, 1996 Issued
Array ( [id] => 3705431 [patent_doc_number] => 05654234 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-05 [patent_title] => 'Method for forming a void-free tungsten-plug contact in the presence of a contact opening overhang' [patent_app_type] => 1 [patent_app_number] => 8/638674 [patent_app_country] => US [patent_app_date] => 1996-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2121 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/654/05654234.pdf [firstpage_image] =>[orig_patent_app_number] => 638674 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/638674
Method for forming a void-free tungsten-plug contact in the presence of a contact opening overhang Apr 28, 1996 Issued
Array ( [id] => 4004607 [patent_doc_number] => 05960312 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Process for forming a contact electrode' [patent_app_type] => 1 [patent_app_number] => 8/638206 [patent_app_country] => US [patent_app_date] => 1996-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2837 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/960/05960312.pdf [firstpage_image] =>[orig_patent_app_number] => 638206 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/638206
Process for forming a contact electrode Apr 25, 1996 Issued
Array ( [id] => 3824398 [patent_doc_number] => 05731225 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'Method for fabricating semiconductor device having buried contact structure' [patent_app_type] => 1 [patent_app_number] => 8/634402 [patent_app_country] => US [patent_app_date] => 1996-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2598 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/731/05731225.pdf [firstpage_image] =>[orig_patent_app_number] => 634402 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/634402
Method for fabricating semiconductor device having buried contact structure Apr 17, 1996 Issued
08/634492 METAL INTERCONNECT STRUCTURE FOR AN INTEGATED CIRCUIT WITH IMPROVED ELECTROMIGRATION RELIABILITY Apr 17, 1996 Abandoned
Array ( [id] => 3889357 [patent_doc_number] => 05834367 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Method of manufacturing semiconductor device having a multilayer wiring' [patent_app_type] => 1 [patent_app_number] => 8/629944 [patent_app_country] => US [patent_app_date] => 1996-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 17 [patent_no_of_words] => 3290 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/834/05834367.pdf [firstpage_image] =>[orig_patent_app_number] => 629944 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/629944
Method of manufacturing semiconductor device having a multilayer wiring Apr 11, 1996 Issued
Array ( [id] => 3695786 [patent_doc_number] => 05595937 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-21 [patent_title] => 'Method for fabricating semiconductor device with interconnections buried in trenches' [patent_app_type] => 1 [patent_app_number] => 8/635230 [patent_app_country] => US [patent_app_date] => 1996-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 45 [patent_no_of_words] => 6294 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/595/05595937.pdf [firstpage_image] =>[orig_patent_app_number] => 635230 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/635230
Method for fabricating semiconductor device with interconnections buried in trenches Apr 11, 1996 Issued
Array ( [id] => 3999663 [patent_doc_number] => 05950099 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Method of forming an interconnect' [patent_app_type] => 1 [patent_app_number] => 8/629442 [patent_app_country] => US [patent_app_date] => 1996-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 2427 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/950/05950099.pdf [firstpage_image] =>[orig_patent_app_number] => 629442 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/629442
Method of forming an interconnect Apr 8, 1996 Issued
Array ( [id] => 3705171 [patent_doc_number] => 05654216 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-05 [patent_title] => 'Formation of a metal via structure from a composite metal layer' [patent_app_type] => 1 [patent_app_number] => 8/630708 [patent_app_country] => US [patent_app_date] => 1996-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3123 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 541 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/654/05654216.pdf [firstpage_image] =>[orig_patent_app_number] => 630708 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/630708
Formation of a metal via structure from a composite metal layer Apr 7, 1996 Issued
Array ( [id] => 3705415 [patent_doc_number] => 05654233 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-05 [patent_title] => 'Step coverage enhancement process for sub half micron contact/via' [patent_app_type] => 1 [patent_app_number] => 8/630710 [patent_app_country] => US [patent_app_date] => 1996-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2853 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/654/05654233.pdf [firstpage_image] =>[orig_patent_app_number] => 630710 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/630710
Step coverage enhancement process for sub half micron contact/via Apr 7, 1996 Issued
Array ( [id] => 3877101 [patent_doc_number] => 05728625 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-17 [patent_title] => 'Process for device fabrication in which a thin layer of cobalt silicide is formed' [patent_app_type] => 1 [patent_app_number] => 8/627560 [patent_app_country] => US [patent_app_date] => 1996-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 5820 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/728/05728625.pdf [firstpage_image] =>[orig_patent_app_number] => 627560 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/627560
Process for device fabrication in which a thin layer of cobalt silicide is formed Apr 3, 1996 Issued
Array ( [id] => 3760597 [patent_doc_number] => 05851917 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-22 [patent_title] => 'Method for manufacturing a multi-layer wiring structure of a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/625114 [patent_app_country] => US [patent_app_date] => 1996-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 31 [patent_no_of_words] => 12465 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/851/05851917.pdf [firstpage_image] =>[orig_patent_app_number] => 625114 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/625114
Method for manufacturing a multi-layer wiring structure of a semiconductor device Mar 31, 1996 Issued
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