Application number | Title of the application | Filing Date | Status |
---|
Array
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[patent_doc_number] => 05861322
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[patent_kind] => NA
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[patent_title] => 'Process for manufacturing an interconnection substrate to connect a chip onto a reception substrate'
[patent_app_type] => 1
[patent_app_number] => 8/658684
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Array
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[id] => 3894691
[patent_doc_number] => 05750438
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-12
[patent_title] => 'Method for fabricating a local interconnection structure'
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[patent_app_number] => 8/658032
[patent_app_country] => US
[patent_app_date] => 1996-06-04
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/658032 | Method for fabricating a local interconnection structure | Jun 3, 1996 | Issued |
Array
(
[id] => 4107708
[patent_doc_number] => 06057215
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-05-02
[patent_title] => 'Process for forming a refractory metal silicide film having a uniform thickness'
[patent_app_type] => 1
[patent_app_number] => 8/660186
[patent_app_country] => US
[patent_app_date] => 1996-05-31
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08/654755 | PROCESS FOR FABRICATING CONNECTION STRUCTURES | May 28, 1996 | Abandoned |
Array
(
[id] => 3681981
[patent_doc_number] => 05633200
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-27
[patent_title] => 'Process for manufacturing a large grain tungsten nitride film and process for manufacturing a lightly nitrided titanium salicide diffusion barrier with a large grain tungsten nitride cover layer'
[patent_app_type] => 1
[patent_app_number] => 8/653428
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08/657056 | METHOD OF PREVENTING ALUMINUM SPUTTERING DURING OXIDE VIA ETCHING | May 23, 1996 | Abandoned |
08/650356 | ALCU METAL DEPOSITION FOR ROBUST RC VIA PERFORMANCE | May 19, 1996 | Abandoned |
Array
(
[id] => 3730108
[patent_doc_number] => 05693561
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[patent_kind] => NA
[patent_issue_date] => 1997-12-02
[patent_title] => 'Method of integrated circuit fabrication including a step of depositing tungsten'
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[patent_app_number] => 8/645852
[patent_app_country] => US
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Array
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-24
[patent_title] => 'Method for manufacturing a semiconductor device having interconnection layers'
[patent_app_type] => 1
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Array
(
[id] => 3705431
[patent_doc_number] => 05654234
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-05
[patent_title] => 'Method for forming a void-free tungsten-plug contact in the presence of a contact opening overhang'
[patent_app_type] => 1
[patent_app_number] => 8/638674
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/638674 | Method for forming a void-free tungsten-plug contact in the presence of a contact opening overhang | Apr 28, 1996 | Issued |
Array
(
[id] => 4004607
[patent_doc_number] => 05960312
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-28
[patent_title] => 'Process for forming a contact electrode'
[patent_app_type] => 1
[patent_app_number] => 8/638206
[patent_app_country] => US
[patent_app_date] => 1996-04-26
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[firstpage_image] =>[orig_patent_app_number] => 638206
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/638206 | Process for forming a contact electrode | Apr 25, 1996 | Issued |
Array
(
[id] => 3824398
[patent_doc_number] => 05731225
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-24
[patent_title] => 'Method for fabricating semiconductor device having buried contact structure'
[patent_app_type] => 1
[patent_app_number] => 8/634402
[patent_app_country] => US
[patent_app_date] => 1996-04-18
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[firstpage_image] =>[orig_patent_app_number] => 634402
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/634402 | Method for fabricating semiconductor device having buried contact structure | Apr 17, 1996 | Issued |
08/634492 | METAL INTERCONNECT STRUCTURE FOR AN INTEGATED CIRCUIT WITH IMPROVED ELECTROMIGRATION RELIABILITY | Apr 17, 1996 | Abandoned |
Array
(
[id] => 3889357
[patent_doc_number] => 05834367
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-10
[patent_title] => 'Method of manufacturing semiconductor device having a multilayer wiring'
[patent_app_type] => 1
[patent_app_number] => 8/629944
[patent_app_country] => US
[patent_app_date] => 1996-04-12
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/629944 | Method of manufacturing semiconductor device having a multilayer wiring | Apr 11, 1996 | Issued |
Array
(
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[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-21
[patent_title] => 'Method for fabricating semiconductor device with interconnections buried in trenches'
[patent_app_type] => 1
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[patent_app_date] => 1996-04-12
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Array
(
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Array
(
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[patent_kind] => NA
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/630708 | Formation of a metal via structure from a composite metal layer | Apr 7, 1996 | Issued |
Array
(
[id] => 3705415
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[patent_kind] => NA
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/630710 | Step coverage enhancement process for sub half micron contact/via | Apr 7, 1996 | Issued |
Array
(
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[patent_kind] => NA
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/625114 | Method for manufacturing a multi-layer wiring structure of a semiconductor device | Mar 31, 1996 | Issued |