Search

Barbara J Bullock

Examiner (ID: 9881)

Most Active Art Unit
2901
Art Unit(s)
2900, 2912, 2901, 2902
Total Applications
4468
Issued Applications
4372
Pending Applications
0
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
08/596228 SEMICONDUCTOR DEVICE HAVING VERY LOW CONTACT RESISTANCE AND VERY SHALLOW CONTACT STRUCTURE Mar 25, 1996 Abandoned
Array ( [id] => 3937295 [patent_doc_number] => 05915204 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'Method of manufacturing a semiconductor device including a metal silicide layer' [patent_app_type] => 1 [patent_app_number] => 8/621976 [patent_app_country] => US [patent_app_date] => 1996-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 7192 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/915/05915204.pdf [firstpage_image] =>[orig_patent_app_number] => 621976 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/621976
Method of manufacturing a semiconductor device including a metal silicide layer Mar 25, 1996 Issued
Array ( [id] => 3694424 [patent_doc_number] => 05661052 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-26 [patent_title] => 'Method of fabricating semiconductor device having low-resistance gate electrode and diffusion layers' [patent_app_type] => 1 [patent_app_number] => 8/617686 [patent_app_country] => US [patent_app_date] => 1996-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 33 [patent_no_of_words] => 6168 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/661/05661052.pdf [firstpage_image] =>[orig_patent_app_number] => 617686 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/617686
Method of fabricating semiconductor device having low-resistance gate electrode and diffusion layers Mar 18, 1996 Issued
Array ( [id] => 4182576 [patent_doc_number] => 06150247 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Method for making polycide-to-polycide low contact resistance contacts for interconnections on integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/590548 [patent_app_country] => US [patent_app_date] => 1996-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4333 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150247.pdf [firstpage_image] =>[orig_patent_app_number] => 590548 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/590548
Method for making polycide-to-polycide low contact resistance contacts for interconnections on integrated circuits Mar 18, 1996 Issued
Array ( [id] => 3705401 [patent_doc_number] => 05654232 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-05 [patent_title] => 'Wetting layer sidewalls to promote copper reflow into grooves' [patent_app_type] => 1 [patent_app_number] => 8/617980 [patent_app_country] => US [patent_app_date] => 1996-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 5488 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/654/05654232.pdf [firstpage_image] =>[orig_patent_app_number] => 617980 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/617980
Wetting layer sidewalls to promote copper reflow into grooves Mar 14, 1996 Issued
Array ( [id] => 3727969 [patent_doc_number] => 05652160 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-29 [patent_title] => 'Method of fabricating a buried contact structure with WSi.sub.x sidewall spacers' [patent_app_type] => 1 [patent_app_number] => 8/613092 [patent_app_country] => US [patent_app_date] => 1996-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 1882 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/652/05652160.pdf [firstpage_image] =>[orig_patent_app_number] => 613092 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/613092
Method of fabricating a buried contact structure with WSi.sub.x sidewall spacers Mar 7, 1996 Issued
Array ( [id] => 3727237 [patent_doc_number] => 05670427 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-23 [patent_title] => 'Method for forming metal contacts in semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 8/610716 [patent_app_country] => US [patent_app_date] => 1996-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 1981 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/670/05670427.pdf [firstpage_image] =>[orig_patent_app_number] => 610716 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/610716
Method for forming metal contacts in semiconductor devices Mar 3, 1996 Issued
Array ( [id] => 4322115 [patent_doc_number] => 06331485 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Method of producing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/606975 [patent_app_country] => US [patent_app_date] => 1996-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2842 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/331/06331485.pdf [firstpage_image] =>[orig_patent_app_number] => 606975 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/606975
Method of producing semiconductor device Feb 25, 1996 Issued
Array ( [id] => 3982874 [patent_doc_number] => 05861340 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-19 [patent_title] => 'Method of forming a polycide film' [patent_app_type] => 1 [patent_app_number] => 8/602126 [patent_app_country] => US [patent_app_date] => 1996-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3614 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/861/05861340.pdf [firstpage_image] =>[orig_patent_app_number] => 602126 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/602126
Method of forming a polycide film Feb 14, 1996 Issued
Array ( [id] => 3768233 [patent_doc_number] => 05773347 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Method of maufacturing field effect transistor' [patent_app_type] => 1 [patent_app_number] => 8/601543 [patent_app_country] => US [patent_app_date] => 1996-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 46 [patent_no_of_words] => 7530 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/773/05773347.pdf [firstpage_image] =>[orig_patent_app_number] => 601543 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/601543
Method of maufacturing field effect transistor Feb 13, 1996 Issued
Array ( [id] => 3663424 [patent_doc_number] => 05668040 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-16 [patent_title] => 'Method for forming a semiconductor device electrode which also serves as a diffusion barrier' [patent_app_type] => 1 [patent_app_number] => 8/601621 [patent_app_country] => US [patent_app_date] => 1996-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3273 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/668/05668040.pdf [firstpage_image] =>[orig_patent_app_number] => 601621 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/601621
Method for forming a semiconductor device electrode which also serves as a diffusion barrier Feb 13, 1996 Issued
Array ( [id] => 3660239 [patent_doc_number] => 05656519 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-12 [patent_title] => 'Method for manufacturing salicide semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/600532 [patent_app_country] => US [patent_app_date] => 1996-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 48 [patent_no_of_words] => 4939 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/656/05656519.pdf [firstpage_image] =>[orig_patent_app_number] => 600532 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/600532
Method for manufacturing salicide semiconductor device Feb 12, 1996 Issued
Array ( [id] => 3881853 [patent_doc_number] => 05798298 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-25 [patent_title] => 'Method of automatically generating dummy metals for multilevel interconnection' [patent_app_type] => 1 [patent_app_number] => 8/598802 [patent_app_country] => US [patent_app_date] => 1996-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 2323 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/798/05798298.pdf [firstpage_image] =>[orig_patent_app_number] => 598802 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/598802
Method of automatically generating dummy metals for multilevel interconnection Feb 8, 1996 Issued
Array ( [id] => 3705209 [patent_doc_number] => 05654219 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-05 [patent_title] => 'Annealed poly-silicide etch process' [patent_app_type] => 1 [patent_app_number] => 8/605310 [patent_app_country] => US [patent_app_date] => 1996-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 2900 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/654/05654219.pdf [firstpage_image] =>[orig_patent_app_number] => 605310 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/605310
Annealed poly-silicide etch process Feb 6, 1996 Issued
08/595704 METHOD FOR IMPROVED ALUMINUM-COPPER DEPOSITION AND ROBUST VIA CONTACT RESISTANCE Feb 1, 1996 Abandoned
08/593856 METHOD OF FORMING LOW RESISTANCE CONTACT STRUCTURES IN VIAS ARRANGED BETWEEN TWO LEVELS OF INTERCONNECT LINES Jan 29, 1996 Abandoned
Array ( [id] => 3826320 [patent_doc_number] => 05759899 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Method of fabricating semiconductor device having a salicide structure' [patent_app_type] => 1 [patent_app_number] => 8/592992 [patent_app_country] => US [patent_app_date] => 1996-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 25 [patent_no_of_words] => 9975 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/759/05759899.pdf [firstpage_image] =>[orig_patent_app_number] => 592992 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/592992
Method of fabricating semiconductor device having a salicide structure Jan 28, 1996 Issued
08/599506 PROCESS FOR PRODUCING A HIGH PERFORMANCE BIPOLAR STRUCTURE Jan 24, 1996 Abandoned
Array ( [id] => 3728301 [patent_doc_number] => 05652181 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-29 [patent_title] => 'Thermal process for forming high value resistors' [patent_app_type] => 1 [patent_app_number] => 8/585084 [patent_app_country] => US [patent_app_date] => 1996-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2173 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/652/05652181.pdf [firstpage_image] =>[orig_patent_app_number] => 585084 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/585084
Thermal process for forming high value resistors Jan 15, 1996 Issued
08/583790 MODIFIED TUNGSTEN-PLUG CONTACT PROCESS Jan 10, 1996 Abandoned
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