Barbara J Bullock

Array ( [id] => 3693167 [patent_doc_number] => 05679606 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'method of forming inter-metal-dielectric structure' [patent_app_type] => 1 [patent_app_number] => 8/579518 [patent_app_country] => US [patent_app_date] => 1995-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3841 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/679/05679606.pdf [firstpage_image] =>[orig_patent_app_number] => 579518 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3884796 [patent_doc_number] => 05776831 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Method of forming a high electromigration resistant metallization system' [patent_app_type] => 1 [patent_app_number] => 8/578118 [patent_app_country] => US [patent_app_date] => 1995-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 4404 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/776/05776831.pdf [firstpage_image] =>[orig_patent_app_number] => 578118 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3950453 [patent_doc_number] => 05899720 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Process of fabricating salicide structure from high-purity reproducible cobalt layer without sacrifice of leakage current and breakdown voltage of P-N junction' [patent_app_type] => 1 [patent_app_number] => 8/577748 [patent_app_country] => US [patent_app_date] => 1995-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 6639 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/899/05899720.pdf [firstpage_image] =>[orig_patent_app_number] => 577748 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3786181 [patent_doc_number] => 05736455 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Method for passivating the sidewalls of a tungsten word line' [patent_app_type] => 1 [patent_app_number] => 8/577856 [patent_app_country] => US [patent_app_date] => 1995-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2013 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/736/05736455.pdf [firstpage_image] =>[orig_patent_app_number] => 577856 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3886154 [patent_doc_number] => 05893749 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Method for forming a hole filling plug for a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/575478 [patent_app_country] => US [patent_app_date] => 1995-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4058 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/893/05893749.pdf [firstpage_image] =>[orig_patent_app_number] => 575478 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3774227 [patent_doc_number] => 05817573 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Semiconductor processing method of providing an electrically conductive interconnecting plug between an elevationally inner electrically conductive node and an elevationally outer electrically conductive node' [patent_app_type] => 1 [patent_app_number] => 8/569283 [patent_app_country] => US [patent_app_date] => 1995-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2476 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/817/05817573.pdf [firstpage_image] =>[orig_patent_app_number] => 569283 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3529535 [patent_doc_number] => 05583065 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-10 [patent_title] => 'Method of making a MOS semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/568407 [patent_app_country] => US [patent_app_date] => 1995-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2532 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 388 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/583/05583065.pdf [firstpage_image] =>[orig_patent_app_number] => 568407 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3768217 [patent_doc_number] => 05773346 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Semiconductor processing method of forming a buried contact' [patent_app_type] => 1 [patent_app_number] => 8/567916 [patent_app_country] => US [patent_app_date] => 1995-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 2594 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/773/05773346.pdf [firstpage_image] =>[orig_patent_app_number] => 567916 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3657805 [patent_doc_number] => 05627101 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-06 [patent_title] => 'Method of fabricating polysilicon electromigration sensor which can detect and monitor electromigration in composite metal lines on integrated circuit structures' [patent_app_type] => 1 [patent_app_number] => 8/566808 [patent_app_country] => US [patent_app_date] => 1995-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3039 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/627/05627101.pdf [firstpage_image] =>[orig_patent_app_number] => 566808 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3723619 [patent_doc_number] => 05681778 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'Semiconductor processing method of forming a buried contact and conductive line' [patent_app_type] => 1 [patent_app_number] => 8/562928 [patent_app_country] => US [patent_app_date] => 1995-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 2412 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/681/05681778.pdf [firstpage_image] =>[orig_patent_app_number] => 562928 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3665632 [patent_doc_number] => 05599740 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-04 [patent_title] => 'Deposit-etch-deposit ozone/teos insulator layer method' [patent_app_type] => 1 [patent_app_number] => 8/558491 [patent_app_country] => US [patent_app_date] => 1995-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6848 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/599/05599740.pdf [firstpage_image] =>[orig_patent_app_number] => 558491 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3647225 [patent_doc_number] => 05629238 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-13 [patent_title] => 'Method for forming conductive line of semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/557534 [patent_app_country] => US [patent_app_date] => 1995-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 2653 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/629/05629238.pdf [firstpage_image] =>[orig_patent_app_number] => 557534 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3870148 [patent_doc_number] => 05763321 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Method of manufacturing semiconductor device utilizing selective CVD method' [patent_app_type] => 1 [patent_app_number] => 8/554753 [patent_app_country] => US [patent_app_date] => 1995-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 6674 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/763/05763321.pdf [firstpage_image] =>[orig_patent_app_number] => 554753 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3546955 [patent_doc_number] => 05545591 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-13 [patent_title] => 'Method for forming an aluminum film used as an interconnect in a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/554029 [patent_app_country] => US [patent_app_date] => 1995-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2072 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/545/05545591.pdf [firstpage_image] =>[orig_patent_app_number] => 554029 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3849381 [patent_doc_number] => 05767001 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Process for producing semiconductor components between which contact is made vertically' [patent_app_type] => 1 [patent_app_number] => 8/545650 [patent_app_country] => US [patent_app_date] => 1995-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2471 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/767/05767001.pdf [firstpage_image] =>[orig_patent_app_number] => 545650 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3760579 [patent_doc_number] => 05851916 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-22 [patent_title] => 'Formation of a self-aligned integrated circuit structures using planarization to form a top surface' [patent_app_type] => 1 [patent_app_number] => 8/552824 [patent_app_country] => US [patent_app_date] => 1995-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 2805 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/851/05851916.pdf [firstpage_image] =>[orig_patent_app_number] => 552824 [rel_patent_id] =>[rel_patent_doc_number] =>)