Barbara J Bullock
Examiner (ID: 9881)
Most Active Art Unit | 2901 |
Art Unit(s) | 2900, 2912, 2901, 2902 |
Total Applications | 4468 |
Issued Applications | 4372 |
Pending Applications | 0 |
Abandoned Applications | 96 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 4417376
[patent_doc_number] => 06194296
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-27
[patent_title] => 'Method for making planarized polycide'
[patent_app_type] => 1
[patent_app_number] => 8/558564
[patent_app_country] => US
[patent_app_date] => 1995-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 17
[patent_no_of_words] => 4235
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/194/06194296.pdf
[firstpage_image] =>[orig_patent_app_number] => 558564
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/558564 | Method for making planarized polycide | Oct 30, 1995 | Issued |
Array
(
[id] => 3815339
[patent_doc_number] => 05770495
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-23
[patent_title] => 'Method of fabricating semiconductor device including high temperature heat treatment'
[patent_app_type] => 1
[patent_app_number] => 8/548913
[patent_app_country] => US
[patent_app_date] => 1995-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 12
[patent_no_of_words] => 6451
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/770/05770495.pdf
[firstpage_image] =>[orig_patent_app_number] => 548913
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/548913 | Method of fabricating semiconductor device including high temperature heat treatment | Oct 25, 1995 | Issued |
Array
(
[id] => 3587225
[patent_doc_number] => 05550071
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-27
[patent_title] => 'Method for forming micro contacts of semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/546736
[patent_app_country] => US
[patent_app_date] => 1995-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 1809
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 387
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/550/05550071.pdf
[firstpage_image] =>[orig_patent_app_number] => 546736
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/546736 | Method for forming micro contacts of semiconductor device | Oct 22, 1995 | Issued |
Array
(
[id] => 3647198
[patent_doc_number] => 05629237
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-13
[patent_title] => 'Taper etching without re-entrance profile'
[patent_app_type] => 1
[patent_app_number] => 8/545380
[patent_app_country] => US
[patent_app_date] => 1995-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 2212
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/629/05629237.pdf
[firstpage_image] =>[orig_patent_app_number] => 545380
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/545380 | Taper etching without re-entrance profile | Oct 18, 1995 | Issued |
Array
(
[id] => 3681997
[patent_doc_number] => 05633201
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-27
[patent_title] => 'Method for forming tungsten plugs in contact holes of a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/538466
[patent_app_country] => US
[patent_app_date] => 1995-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 2413
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 243
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/633/05633201.pdf
[firstpage_image] =>[orig_patent_app_number] => 538466
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/538466 | Method for forming tungsten plugs in contact holes of a semiconductor device | Oct 2, 1995 | Issued |
08/537378 | SEMICONDUCTOR DEVICE HAVING A PHOSPHORUS DOPED PECVD FILM AND A METHODOF MANUFACTURE | Oct 1, 1995 | Abandoned |
Array
(
[id] => 3768122
[patent_doc_number] => 05773339
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-30
[patent_title] => 'Method of making diffused layer resistors for semiconductor devices'
[patent_app_type] => 1
[patent_app_number] => 8/534246
[patent_app_country] => US
[patent_app_date] => 1995-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 17
[patent_no_of_words] => 5613
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/773/05773339.pdf
[firstpage_image] =>[orig_patent_app_number] => 534246
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/534246 | Method of making diffused layer resistors for semiconductor devices | Sep 25, 1995 | Issued |
Array
(
[id] => 3589721
[patent_doc_number] => 05567652
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-22
[patent_title] => 'Method for manufacturing semiconductor device comprising cobalt silicide film'
[patent_app_type] => 1
[patent_app_number] => 8/533160
[patent_app_country] => US
[patent_app_date] => 1995-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 13
[patent_no_of_words] => 2907
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/567/05567652.pdf
[firstpage_image] =>[orig_patent_app_number] => 533160
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/533160 | Method for manufacturing semiconductor device comprising cobalt silicide film | Sep 24, 1995 | Issued |
Array
(
[id] => 3768057
[patent_doc_number] => 05773334
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-30
[patent_title] => 'Method of manufacturing a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/531606
[patent_app_country] => US
[patent_app_date] => 1995-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 39
[patent_no_of_words] => 7251
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/773/05773334.pdf
[firstpage_image] =>[orig_patent_app_number] => 531606
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/531606 | Method of manufacturing a semiconductor device | Sep 20, 1995 | Issued |
Array
(
[id] => 3791852
[patent_doc_number] => 05726098
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-10
[patent_title] => 'Method of manufacturing semiconductor device having multilevel interconnection'
[patent_app_type] => 1
[patent_app_number] => 8/531376
[patent_app_country] => US
[patent_app_date] => 1995-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 2024
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 253
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/726/05726098.pdf
[firstpage_image] =>[orig_patent_app_number] => 531376
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/531376 | Method of manufacturing semiconductor device having multilevel interconnection | Sep 20, 1995 | Issued |
Array
(
[id] => 3853431
[patent_doc_number] => RE035785
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-05
[patent_title] => 'Low-pressure chemical vapor deposition process for depositing high-density highly-conformal, titanium nitride films of low bulk resistivity'
[patent_app_type] => 2
[patent_app_number] => 8/570613
[patent_app_country] => US
[patent_app_date] => 1995-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2115
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/RE/035/RE035785.pdf
[firstpage_image] =>[orig_patent_app_number] => 570613
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/570613 | Low-pressure chemical vapor deposition process for depositing high-density highly-conformal, titanium nitride films of low bulk resistivity | Sep 20, 1995 | Issued |
Array
(
[id] => 1461802
[patent_doc_number] => RE037865
[patent_country] => US
[patent_kind] => E1
[patent_issue_date] => 2002-10-01
[patent_title] => 'Semiconductor electrical interconnection methods'
[patent_app_type] => E1
[patent_app_number] => 08/528062
[patent_app_country] => US
[patent_app_date] => 1995-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 3901
[patent_no_of_claims] => 43
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 318
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/RE/037/RE037865.pdf
[firstpage_image] =>[orig_patent_app_number] => 08528062
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/528062 | Semiconductor electrical interconnection methods | Sep 13, 1995 | Issued |
Array
(
[id] => 3757065
[patent_doc_number] => 05721155
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-24
[patent_title] => 'Method for forming a via contact of a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/520434
[patent_app_country] => US
[patent_app_date] => 1995-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 2
[patent_no_of_words] => 3621
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/721/05721155.pdf
[firstpage_image] =>[orig_patent_app_number] => 520434
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/520434 | Method for forming a via contact of a semiconductor device | Aug 28, 1995 | Issued |
Array
(
[id] => 3660602
[patent_doc_number] => 05656543
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-12
[patent_title] => 'Fabrication of integrated circuits with borderless vias'
[patent_app_type] => 1
[patent_app_number] => 8/519456
[patent_app_country] => US
[patent_app_date] => 1995-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
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[patent_no_of_words] => 5156
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/656/05656543.pdf
[firstpage_image] =>[orig_patent_app_number] => 519456
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/519456 | Fabrication of integrated circuits with borderless vias | Aug 24, 1995 | Issued |
Array
(
[id] => 3589686
[patent_doc_number] => 05567649
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-22
[patent_title] => 'Method of forming a conductive diffusion barrier'
[patent_app_type] => 1
[patent_app_number] => 8/519159
[patent_app_country] => US
[patent_app_date] => 1995-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 2060
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[patent_no_of_ind_claims] => 1
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/567/05567649.pdf
[firstpage_image] =>[orig_patent_app_number] => 519159
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/519159 | Method of forming a conductive diffusion barrier | Aug 23, 1995 | Issued |
Array
(
[id] => 3553130
[patent_doc_number] => 05518959
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-21
[patent_title] => 'Method for selectively depositing silicon oxide spacer layers'
[patent_app_type] => 1
[patent_app_number] => 8/518706
[patent_app_country] => US
[patent_app_date] => 1995-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/518/05518959.pdf
[firstpage_image] =>[orig_patent_app_number] => 518706
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/518706 | Method for selectively depositing silicon oxide spacer layers | Aug 23, 1995 | Issued |
Array
(
[id] => 3770104
[patent_doc_number] => 05756394
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-26
[patent_title] => 'Self-aligned silicide strap connection of polysilicon layers'
[patent_app_type] => 1
[patent_app_number] => 8/518616
[patent_app_country] => US
[patent_app_date] => 1995-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_ind_claims] => 3
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/756/05756394.pdf
[firstpage_image] =>[orig_patent_app_number] => 518616
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/518616 | Self-aligned silicide strap connection of polysilicon layers | Aug 22, 1995 | Issued |
Array
(
[id] => 3826484
[patent_doc_number] => 05759911
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-02
[patent_title] => 'Self-aligned metallurgy'
[patent_app_type] => 1
[patent_app_number] => 8/517782
[patent_app_country] => US
[patent_app_date] => 1995-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 6253
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/759/05759911.pdf
[firstpage_image] =>[orig_patent_app_number] => 517782
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/517782 | Self-aligned metallurgy | Aug 21, 1995 | Issued |
Array
(
[id] => 3770117
[patent_doc_number] => 05756395
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-26
[patent_title] => 'Process for forming metal interconnect structures for use with integrated circuit devices to form integrated circuit structures'
[patent_app_type] => 1
[patent_app_number] => 8/516614
[patent_app_country] => US
[patent_app_date] => 1995-08-18
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/756/05756395.pdf
[firstpage_image] =>[orig_patent_app_number] => 516614
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/516614 | Process for forming metal interconnect structures for use with integrated circuit devices to form integrated circuit structures | Aug 17, 1995 | Issued |
Array
(
[id] => 3613416
[patent_doc_number] => 05510297
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-23
[patent_title] => 'Process for uniform deposition of tungsten silicide on semiconductor wafers by treatment of susceptor having aluminum nitride surface thereon with tungsten silicide after cleaning of susceptor'
[patent_app_type] => 1
[patent_app_number] => 8/504294
[patent_app_country] => US
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[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/510/05510297.pdf
[firstpage_image] =>[orig_patent_app_number] => 504294
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/504294 | Process for uniform deposition of tungsten silicide on semiconductor wafers by treatment of susceptor having aluminum nitride surface thereon with tungsten silicide after cleaning of susceptor | Aug 9, 1995 | Issued |