Search

Barbara J Bullock

Examiner (ID: 9881)

Most Active Art Unit
2901
Art Unit(s)
2900, 2912, 2901, 2902
Total Applications
4468
Issued Applications
4372
Pending Applications
0
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3695773 [patent_doc_number] => 05595936 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-21 [patent_title] => 'Method for forming contacts in semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/512141 [patent_app_country] => US [patent_app_date] => 1995-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2709 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/595/05595936.pdf [firstpage_image] =>[orig_patent_app_number] => 512141 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/512141
Method for forming contacts in semiconductor device Aug 6, 1995 Issued
08/507545 METHOD FOR FORMATION OF CONTACT PLUGS UTILIZING ETCHBACK Jul 25, 1995 Abandoned
Array ( [id] => 3701298 [patent_doc_number] => 05674780 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-07 [patent_title] => 'Method of forming an electrically conductive polymer bump over an aluminum electrode' [patent_app_type] => 1 [patent_app_number] => 8/505936 [patent_app_country] => US [patent_app_date] => 1995-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2151 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/674/05674780.pdf [firstpage_image] =>[orig_patent_app_number] => 505936 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/505936
Method of forming an electrically conductive polymer bump over an aluminum electrode Jul 23, 1995 Issued
Array ( [id] => 3608072 [patent_doc_number] => 05589419 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-31 [patent_title] => 'Process for fabricating semiconductor device having a multilevel interconnection' [patent_app_type] => 1 [patent_app_number] => 8/505786 [patent_app_country] => US [patent_app_date] => 1995-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3873 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/589/05589419.pdf [firstpage_image] =>[orig_patent_app_number] => 505786 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/505786
Process for fabricating semiconductor device having a multilevel interconnection Jul 20, 1995 Issued
Array ( [id] => 3690922 [patent_doc_number] => 05604155 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-18 [patent_title] => 'Al-based contact formation process using Ti glue layer to prevent nodule-induced bridging' [patent_app_type] => 1 [patent_app_number] => 8/503286 [patent_app_country] => US [patent_app_date] => 1995-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2329 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 335 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/604/05604155.pdf [firstpage_image] =>[orig_patent_app_number] => 503286 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/503286
Al-based contact formation process using Ti glue layer to prevent nodule-induced bridging Jul 16, 1995 Issued
Array ( [id] => 4034812 [patent_doc_number] => 05856234 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-05 [patent_title] => 'Method of fabricating an antifuse' [patent_app_type] => 1 [patent_app_number] => 8/501596 [patent_app_country] => US [patent_app_date] => 1995-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 5032 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/856/05856234.pdf [firstpage_image] =>[orig_patent_app_number] => 501596 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/501596
Method of fabricating an antifuse Jul 10, 1995 Issued
Array ( [id] => 3658056 [patent_doc_number] => 05591673 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-07 [patent_title] => 'Tungsten stud process for stacked via applications' [patent_app_type] => 1 [patent_app_number] => 8/498356 [patent_app_country] => US [patent_app_date] => 1995-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2694 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 302 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/591/05591673.pdf [firstpage_image] =>[orig_patent_app_number] => 498356 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/498356
Tungsten stud process for stacked via applications Jul 4, 1995 Issued
Array ( [id] => 3581707 [patent_doc_number] => 05580824 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-03 [patent_title] => 'Method for fabrication of interconnections in semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 8/497396 [patent_app_country] => US [patent_app_date] => 1995-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1534 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/580/05580824.pdf [firstpage_image] =>[orig_patent_app_number] => 497396 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/497396
Method for fabrication of interconnections in semiconductor devices Jun 29, 1995 Issued
Array ( [id] => 3597893 [patent_doc_number] => 05559047 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'Method of reliably manufacturing a semiconductor device having a titanium silicide nitride' [patent_app_type] => 1 [patent_app_number] => 8/496370 [patent_app_country] => US [patent_app_date] => 1995-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 3090 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/559/05559047.pdf [firstpage_image] =>[orig_patent_app_number] => 496370 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/496370
Method of reliably manufacturing a semiconductor device having a titanium silicide nitride Jun 28, 1995 Issued
Array ( [id] => 4237536 [patent_doc_number] => 06090701 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Method for production of semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/521088 [patent_app_country] => US [patent_app_date] => 1995-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 68 [patent_no_of_words] => 31571 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/090/06090701.pdf [firstpage_image] =>[orig_patent_app_number] => 521088 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/521088
Method for production of semiconductor device Jun 19, 1995 Issued
Array ( [id] => 3587333 [patent_doc_number] => 05550079 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-27 [patent_title] => 'Method for fabricating silicide shunt of dual-gate CMOS device' [patent_app_type] => 1 [patent_app_number] => 8/490832 [patent_app_country] => US [patent_app_date] => 1995-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 3438 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/550/05550079.pdf [firstpage_image] =>[orig_patent_app_number] => 490832 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/490832
Method for fabricating silicide shunt of dual-gate CMOS device Jun 14, 1995 Issued
08/489321 PLANARIZED METALLURGY STRUCTURE FOR A SEMICONDUCTOR AND PROCESS OF FABRICATION Jun 11, 1995 Abandoned
Array ( [id] => 3621238 [patent_doc_number] => 05593906 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-14 [patent_title] => 'Method of processing a polysilicon film on a single-crystal silicon substrate' [patent_app_type] => 1 [patent_app_number] => 8/489234 [patent_app_country] => US [patent_app_date] => 1995-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3092 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/593/05593906.pdf [firstpage_image] =>[orig_patent_app_number] => 489234 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/489234
Method of processing a polysilicon film on a single-crystal silicon substrate Jun 11, 1995 Issued
Array ( [id] => 3561408 [patent_doc_number] => 05525552 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-11 [patent_title] => 'Method for fabricating a MOSFET device with a buried contact' [patent_app_type] => 1 [patent_app_number] => 8/488764 [patent_app_country] => US [patent_app_date] => 1995-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2611 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/525/05525552.pdf [firstpage_image] =>[orig_patent_app_number] => 488764 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/488764
Method for fabricating a MOSFET device with a buried contact Jun 7, 1995 Issued
Array ( [id] => 3701191 [patent_doc_number] => 05674774 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-07 [patent_title] => 'Method of making self-aligned remote polysilicon contacts' [patent_app_type] => 1 [patent_app_number] => 8/474794 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 2086 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/674/05674774.pdf [firstpage_image] =>[orig_patent_app_number] => 474794 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/474794
Method of making self-aligned remote polysilicon contacts Jun 6, 1995 Issued
Array ( [id] => 3686771 [patent_doc_number] => 05696018 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-09 [patent_title] => 'Method of forming conductive noble-metal-insulator-alloy barrier layer for high-dielectric-constant material electrodes' [patent_app_type] => 1 [patent_app_number] => 8/487197 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 6719 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/696/05696018.pdf [firstpage_image] =>[orig_patent_app_number] => 487197 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/487197
Method of forming conductive noble-metal-insulator-alloy barrier layer for high-dielectric-constant material electrodes Jun 6, 1995 Issued
Array ( [id] => 4378505 [patent_doc_number] => 06303499 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Process for preparing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/479855 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 9795 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/303/06303499.pdf [firstpage_image] =>[orig_patent_app_number] => 479855 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/479855
Process for preparing semiconductor device Jun 6, 1995 Issued
08/480951 PROCESS FOR FABRICATING CONNECTION STRUCTURES Jun 6, 1995 Abandoned
08/474904 SEMICONDUCTOR DEVICE AND FABRICATION PROCESS THEREFOR Jun 6, 1995 Abandoned
08/472602 SEMICONDUCTOR DEVICE INTERCONNECT LAYOUT METHOD AND STRUCTURE FOR REDUCING PERMATURE ELECTROMIGRATION FAILURE DUE TO HIGH LOCALIZED CURRENT DENSITY Jun 6, 1995 Abandoned
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