Search

Barbara J Bullock

Examiner (ID: 9881)

Most Active Art Unit
2901
Art Unit(s)
2900, 2912, 2901, 2902
Total Applications
4468
Issued Applications
4372
Pending Applications
0
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4031289 [patent_doc_number] => 05963827 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Method for producing via contacts in a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/475762 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 9515 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963827.pdf [firstpage_image] =>[orig_patent_app_number] => 475762 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/475762
Method for producing via contacts in a semiconductor device Jun 6, 1995 Issued
Array ( [id] => 3935422 [patent_doc_number] => 05972786 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Contact hole structure in a semiconductor and formation method therefor' [patent_app_type] => 1 [patent_app_number] => 8/478910 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3588 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/972/05972786.pdf [firstpage_image] =>[orig_patent_app_number] => 478910 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/478910
Contact hole structure in a semiconductor and formation method therefor Jun 6, 1995 Issued
08/479406 HIGH ASPECT RATIO LOW RESISTIVITY LINES/VIAS BY SURFACE DIFFUSION Jun 6, 1995 Abandoned
08/467296 SEMICONDUCTOR DEVICE HAVING MULTILAYERED METALIZATION AND METHOD OF MANUFACTURING THE SAME Jun 5, 1995 Abandoned
08/470302 PRODUCTION WORTHY INTERCONNECT PROCESS FOR DEEP SUB-HALF MICROMETER BACK-END-OF-LINE TECHNOLOGY Jun 5, 1995 Abandoned
08/469974 METHOD FOR MAKING TITANIUM POLY-SIDE CMOS CIRCUIT CONTACTS Jun 5, 1995 Abandoned
Array ( [id] => 3731026 [patent_doc_number] => 05665634 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-09 [patent_title] => 'Method of increasing maximum terminal voltage of a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/463560 [patent_app_country] => US [patent_app_date] => 1995-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1903 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/665/05665634.pdf [firstpage_image] =>[orig_patent_app_number] => 463560 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/463560
Method of increasing maximum terminal voltage of a semiconductor device Jun 4, 1995 Issued
08/461664 METHOD FOR FORMING OHMIC CONTACT Jun 4, 1995 Abandoned
Array ( [id] => 3580808 [patent_doc_number] => 05498571 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-12 [patent_title] => 'Method of manufacturing a semiconductor device having reliable multi-layered wiring' [patent_app_type] => 1 [patent_app_number] => 8/457484 [patent_app_country] => US [patent_app_date] => 1995-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 8 [patent_no_of_words] => 2651 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/498/05498571.pdf [firstpage_image] =>[orig_patent_app_number] => 457484 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/457484
Method of manufacturing a semiconductor device having reliable multi-layered wiring May 31, 1995 Issued
Array ( [id] => 3841198 [patent_doc_number] => 05707883 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-13 [patent_title] => 'Method for manufacturing a semiconductor device using antireflection coating' [patent_app_type] => 1 [patent_app_number] => 8/455480 [patent_app_country] => US [patent_app_date] => 1995-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 35 [patent_no_of_words] => 5996 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/707/05707883.pdf [firstpage_image] =>[orig_patent_app_number] => 455480 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/455480
Method for manufacturing a semiconductor device using antireflection coating May 30, 1995 Issued
Array ( [id] => 3549759 [patent_doc_number] => 05571753 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-05 [patent_title] => 'Method for forming a wiring conductor in semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/455086 [patent_app_country] => US [patent_app_date] => 1995-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 5712 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 474 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/571/05571753.pdf [firstpage_image] =>[orig_patent_app_number] => 455086 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/455086
Method for forming a wiring conductor in semiconductor device May 30, 1995 Issued
Array ( [id] => 3522067 [patent_doc_number] => 05489553 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-06 [patent_title] => 'HF vapor surface treatment for the 03 teos gap filling deposition' [patent_app_type] => 1 [patent_app_number] => 8/450410 [patent_app_country] => US [patent_app_date] => 1995-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1311 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/489/05489553.pdf [firstpage_image] =>[orig_patent_app_number] => 450410 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/450410
HF vapor surface treatment for the 03 teos gap filling deposition May 24, 1995 Issued
Array ( [id] => 3730076 [patent_doc_number] => 05635425 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-03 [patent_title] => 'In-situ N.sub.2 plasma treatment for PE TEOS oxide deposition' [patent_app_type] => 1 [patent_app_number] => 8/450296 [patent_app_country] => US [patent_app_date] => 1995-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 2620 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/635/05635425.pdf [firstpage_image] =>[orig_patent_app_number] => 450296 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/450296
In-situ N.sub.2 plasma treatment for PE TEOS oxide deposition May 24, 1995 Issued
Array ( [id] => 3694785 [patent_doc_number] => 05661078 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-26 [patent_title] => 'Method of manufacturing a semiconductor device having a wiring formed by silver bromide' [patent_app_type] => 1 [patent_app_number] => 8/449674 [patent_app_country] => US [patent_app_date] => 1995-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 1924 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/661/05661078.pdf [firstpage_image] =>[orig_patent_app_number] => 449674 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/449674
Method of manufacturing a semiconductor device having a wiring formed by silver bromide May 23, 1995 Issued
Array ( [id] => 3661118 [patent_doc_number] => 05624867 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-29 [patent_title] => 'Low temperature formation of palladium silicided shallow junctions using implant through metal/silicide technology' [patent_app_type] => 1 [patent_app_number] => 8/448670 [patent_app_country] => US [patent_app_date] => 1995-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 2714 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/624/05624867.pdf [firstpage_image] =>[orig_patent_app_number] => 448670 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/448670
Low temperature formation of palladium silicided shallow junctions using implant through metal/silicide technology May 23, 1995 Issued
Array ( [id] => 3495830 [patent_doc_number] => 05532179 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-02 [patent_title] => 'Method of making a field effect trench transistor having lightly doped epitaxial region on the surface portion thereof' [patent_app_type] => 1 [patent_app_number] => 8/447484 [patent_app_country] => US [patent_app_date] => 1995-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2242 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/532/05532179.pdf [firstpage_image] =>[orig_patent_app_number] => 447484 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/447484
Method of making a field effect trench transistor having lightly doped epitaxial region on the surface portion thereof May 22, 1995 Issued
Array ( [id] => 3690717 [patent_doc_number] => 05604140 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-18 [patent_title] => 'Method for forming fine titanium nitride film and method for fabricating semiconductor element using the same' [patent_app_type] => 1 [patent_app_number] => 8/443570 [patent_app_country] => US [patent_app_date] => 1995-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 31 [patent_no_of_words] => 4961 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/604/05604140.pdf [firstpage_image] =>[orig_patent_app_number] => 443570 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/443570
Method for forming fine titanium nitride film and method for fabricating semiconductor element using the same May 21, 1995 Issued
Array ( [id] => 3546721 [patent_doc_number] => 05545574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-13 [patent_title] => 'Process for forming a semiconductor device having a metal-semiconductor compound' [patent_app_type] => 1 [patent_app_number] => 8/444980 [patent_app_country] => US [patent_app_date] => 1995-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2952 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/545/05545574.pdf [firstpage_image] =>[orig_patent_app_number] => 444980 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/444980
Process for forming a semiconductor device having a metal-semiconductor compound May 18, 1995 Issued
Array ( [id] => 3649312 [patent_doc_number] => 05605852 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-25 [patent_title] => 'Method for fabricating high voltage transistor having trenched termination' [patent_app_type] => 1 [patent_app_number] => 8/444336 [patent_app_country] => US [patent_app_date] => 1995-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 3166 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/605/05605852.pdf [firstpage_image] =>[orig_patent_app_number] => 444336 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/444336
Method for fabricating high voltage transistor having trenched termination May 17, 1995 Issued
Array ( [id] => 3554554 [patent_doc_number] => 05543338 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-06 [patent_title] => 'Method for manufacturing a semiconductor device using a semiconductor-on-insulator substrate' [patent_app_type] => 1 [patent_app_number] => 8/441305 [patent_app_country] => US [patent_app_date] => 1995-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 2637 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/543/05543338.pdf [firstpage_image] =>[orig_patent_app_number] => 441305 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/441305
Method for manufacturing a semiconductor device using a semiconductor-on-insulator substrate May 14, 1995 Issued
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