Application number | Title of the application | Filing Date | Status |
---|
Array
(
[id] => 3493735
[patent_doc_number] => 05508230
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-16
[patent_title] => 'Method for making a semiconductor device with diamond heat dissipation layer'
[patent_app_type] => 1
[patent_app_number] => 8/416236
[patent_app_country] => US
[patent_app_date] => 1995-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 1744
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/508/05508230.pdf
[firstpage_image] =>[orig_patent_app_number] => 416236
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/416236 | Method for making a semiconductor device with diamond heat dissipation layer | Apr 3, 1995 | Issued |
Array
(
[id] => 3492087
[patent_doc_number] => 05536676
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-16
[patent_title] => 'Low temperature formation of silicided shallow junctions by ion implantation into thin silicon films'
[patent_app_type] => 1
[patent_app_number] => 8/415666
[patent_app_country] => US
[patent_app_date] => 1995-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 1821
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/536/05536676.pdf
[firstpage_image] =>[orig_patent_app_number] => 415666
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/415666 | Low temperature formation of silicided shallow junctions by ion implantation into thin silicon films | Apr 2, 1995 | Issued |
Array
(
[id] => 3601650
[patent_doc_number] => 05578524
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-26
[patent_title] => 'Fabrication process of a semiconductor device with a wiring structure'
[patent_app_type] => 1
[patent_app_number] => 8/413868
[patent_app_country] => US
[patent_app_date] => 1995-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 21
[patent_no_of_words] => 5137
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 274
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/578/05578524.pdf
[firstpage_image] =>[orig_patent_app_number] => 413868
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/413868 | Fabrication process of a semiconductor device with a wiring structure | Mar 28, 1995 | Issued |
Array
(
[id] => 3553167
[patent_doc_number] => 05518962
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-21
[patent_title] => 'Planarized interlayer insulating film formed of stacked BPSG film and ozone-teos NSG film in semiconductor device and method for forming the same'
[patent_app_type] => 1
[patent_app_number] => 8/411390
[patent_app_country] => US
[patent_app_date] => 1995-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 4108
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 228
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/518/05518962.pdf
[firstpage_image] =>[orig_patent_app_number] => 411390
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/411390 | Planarized interlayer insulating film formed of stacked BPSG film and ozone-teos NSG film in semiconductor device and method for forming the same | Mar 27, 1995 | Issued |
Array
(
[id] => 1462589
[patent_doc_number] => 06350676
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-26
[patent_title] => 'Method of forming high-stability metallic contacts in an integrated circuit with one or more metallized layers'
[patent_app_type] => B1
[patent_app_number] => 08/411385
[patent_app_country] => US
[patent_app_date] => 1995-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 2622
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/350/06350676.pdf
[firstpage_image] =>[orig_patent_app_number] => 08411385
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/411385 | Method of forming high-stability metallic contacts in an integrated circuit with one or more metallized layers | Mar 27, 1995 | Issued |
Array
(
[id] => 3505163
[patent_doc_number] => 05514625
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-07
[patent_title] => 'Method of forming a wiring layer'
[patent_app_type] => 1
[patent_app_number] => 8/404606
[patent_app_country] => US
[patent_app_date] => 1995-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 30
[patent_no_of_words] => 4392
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/514/05514625.pdf
[firstpage_image] =>[orig_patent_app_number] => 404606
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/404606 | Method of forming a wiring layer | Mar 14, 1995 | Issued |
Array
(
[id] => 4405162
[patent_doc_number] => 06271120
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-07
[patent_title] => 'Method of enhanced silicide layer for advanced metal diffusion barrier layer application'
[patent_app_type] => 1
[patent_app_number] => 8/402252
[patent_app_country] => US
[patent_app_date] => 1995-03-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 1513
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 229
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/271/06271120.pdf
[firstpage_image] =>[orig_patent_app_number] => 402252
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/402252 | Method of enhanced silicide layer for advanced metal diffusion barrier layer application | Mar 9, 1995 | Issued |
Array
(
[id] => 3612837
[patent_doc_number] => 05534461
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-09
[patent_title] => 'Method for manufacturing a semiconductor device having planarized wiring'
[patent_app_type] => 1
[patent_app_number] => 8/397616
[patent_app_country] => US
[patent_app_date] => 1995-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 21
[patent_no_of_words] => 5189
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/534/05534461.pdf
[firstpage_image] =>[orig_patent_app_number] => 397616
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/397616 | Method for manufacturing a semiconductor device having planarized wiring | Mar 1, 1995 | Issued |
Array
(
[id] => 1179996
[patent_doc_number] => 06740573
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-05-25
[patent_title] => 'Method for forming an integrated circuit interconnect using a dual poly process'
[patent_app_type] => B2
[patent_app_number] => 08/390714
[patent_app_country] => US
[patent_app_date] => 1995-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 19
[patent_no_of_words] => 2607
[patent_no_of_claims] => 50
[patent_no_of_ind_claims] => 14
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/740/06740573.pdf
[firstpage_image] =>[orig_patent_app_number] => 08390714
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/390714 | Method for forming an integrated circuit interconnect using a dual poly process | Feb 16, 1995 | Issued |
08/389412 | METHOD FOR FABRICATING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING STEP OF FORMING SELF-ALIGNED METAL SILICIDE FILM | Feb 15, 1995 | Abandoned |
Array
(
[id] => 3621143
[patent_doc_number] => 05685946
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-11
[patent_title] => 'Method of producing buried porous silicon-geramanium layers in monocrystalline silicon lattices'
[patent_app_type] => 1
[patent_app_number] => 8/390456
[patent_app_country] => US
[patent_app_date] => 1995-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 4763
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/685/05685946.pdf
[firstpage_image] =>[orig_patent_app_number] => 390456
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/390456 | Method of producing buried porous silicon-geramanium layers in monocrystalline silicon lattices | Feb 14, 1995 | Issued |
Array
(
[id] => 3570863
[patent_doc_number] => 05538922
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-23
[patent_title] => 'Method for forming contact to a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/378990
[patent_app_country] => US
[patent_app_date] => 1995-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 12
[patent_no_of_words] => 4797
[patent_no_of_claims] => 62
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/538/05538922.pdf
[firstpage_image] =>[orig_patent_app_number] => 378990
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/378990 | Method for forming contact to a semiconductor device | Jan 24, 1995 | Issued |
Array
(
[id] => 3460905
[patent_doc_number] => 05468665
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-21
[patent_title] => 'Process for making a semiconductor MOS transistor employing a temporary spacer'
[patent_app_type] => 1
[patent_app_number] => 8/376514
[patent_app_country] => US
[patent_app_date] => 1995-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 29
[patent_no_of_words] => 6235
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/468/05468665.pdf
[firstpage_image] =>[orig_patent_app_number] => 376514
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/376514 | Process for making a semiconductor MOS transistor employing a temporary spacer | Jan 22, 1995 | Issued |
08/375218 | METHOD OF PREVENTING ALUMINUM SPUTTERING DURING OXIDE VIA ETCHING | Jan 18, 1995 | Abandoned |
Array
(
[id] => 3658028
[patent_doc_number] => 05591671
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-07
[patent_title] => 'Method for interconnecting layers in semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/374412
[patent_app_country] => US
[patent_app_date] => 1995-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 16
[patent_no_of_words] => 3363
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/591/05591671.pdf
[firstpage_image] =>[orig_patent_app_number] => 374412
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/374412 | Method for interconnecting layers in semiconductor device | Jan 17, 1995 | Issued |
Array
(
[id] => 3549747
[patent_doc_number] => 05571752
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-05
[patent_title] => 'Method of forming a planar contact with a void'
[patent_app_type] => 1
[patent_app_number] => 8/370456
[patent_app_country] => US
[patent_app_date] => 1995-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 1921
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/571/05571752.pdf
[firstpage_image] =>[orig_patent_app_number] => 370456
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/370456 | Method of forming a planar contact with a void | Jan 8, 1995 | Issued |
Array
(
[id] => 3728328
[patent_doc_number] => 05652183
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-29
[patent_title] => 'Method for fabricating semiconductor device containing excessive silicon in metal silicide film'
[patent_app_type] => 1
[patent_app_number] => 8/368604
[patent_app_country] => US
[patent_app_date] => 1995-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 23
[patent_no_of_words] => 6828
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/652/05652183.pdf
[firstpage_image] =>[orig_patent_app_number] => 368604
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/368604 | Method for fabricating semiconductor device containing excessive silicon in metal silicide film | Jan 3, 1995 | Issued |
Array
(
[id] => 3665590
[patent_doc_number] => 05599737
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-04
[patent_title] => 'Conductive runner fabrication'
[patent_app_type] => 1
[patent_app_number] => 8/367380
[patent_app_country] => US
[patent_app_date] => 1994-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 878
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/599/05599737.pdf
[firstpage_image] =>[orig_patent_app_number] => 367380
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/367380 | Conductive runner fabrication | Dec 29, 1994 | Issued |
Array
(
[id] => 3814908
[patent_doc_number] => 05770464
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-23
[patent_title] => 'Method for fabricating semiconductor devices having lightly doped drain'
[patent_app_type] => 1
[patent_app_number] => 8/365954
[patent_app_country] => US
[patent_app_date] => 1994-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 2110
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 399
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/770/05770464.pdf
[firstpage_image] =>[orig_patent_app_number] => 365954
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/365954 | Method for fabricating semiconductor devices having lightly doped drain | Dec 28, 1994 | Issued |
Array
(
[id] => 3597972
[patent_doc_number] => 05559052
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-09-24
[patent_title] => 'Integrated circuit fabrication with interlevel dielectric'
[patent_app_type] => 1
[patent_app_number] => 8/366192
[patent_app_country] => US
[patent_app_date] => 1994-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 962
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/559/05559052.pdf
[firstpage_image] =>[orig_patent_app_number] => 366192
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/366192 | Integrated circuit fabrication with interlevel dielectric | Dec 28, 1994 | Issued |