Search

Barbara J Bullock

Examiner (ID: 9881)

Most Active Art Unit
2901
Art Unit(s)
2900, 2912, 2901, 2902
Total Applications
4468
Issued Applications
4372
Pending Applications
0
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
08/327588 TAPER ETCHING WITHOUT RE-ENTRANCE PROFILE Oct 23, 1994 Abandoned
Array ( [id] => 3625074 [patent_doc_number] => 05620925 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-15 [patent_title] => 'Method of manufacturing semiconductor device using a hagolen plasma treatment step' [patent_app_type] => 1 [patent_app_number] => 8/327450 [patent_app_country] => US [patent_app_date] => 1994-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 5277 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/620/05620925.pdf [firstpage_image] =>[orig_patent_app_number] => 327450 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/327450
Method of manufacturing semiconductor device using a hagolen plasma treatment step Oct 20, 1994 Issued
Array ( [id] => 3519111 [patent_doc_number] => 05529953 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'Method of forming studs and interconnects in a multi-layered semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/321896 [patent_app_country] => US [patent_app_date] => 1994-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 29 [patent_no_of_words] => 3765 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/529/05529953.pdf [firstpage_image] =>[orig_patent_app_number] => 321896 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/321896
Method of forming studs and interconnects in a multi-layered semiconductor device Oct 13, 1994 Issued
08/322546 MANUFACTURE OF SEMICONDUCTOR DEVICE WITH SALICIDE ELECTRODE Oct 12, 1994 Abandoned
08/322906 DMOS TRANSISTOR WITH LOW ON-RESISTANCE AND METHOD OF FABRICATION Oct 12, 1994 Abandoned
08/321560 METHOD OF MAKING OHMIC CONTACT BETWEEN A THIN FILM POLYSILICON LAYER AND A SUBSEQUENTLY PROVIDED CONDUCTIVE LAYER AND INTEGRATED CIRCUITRY Oct 11, 1994 Abandoned
08/319730 FABRICATION PROCESS FOR SEMICONDUCTOR DEVICE Oct 6, 1994 Abandoned
Array ( [id] => 3623084 [patent_doc_number] => 05607877 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-04 [patent_title] => 'Projection-electrode fabrication method' [patent_app_type] => 1 [patent_app_number] => 8/321013 [patent_app_country] => US [patent_app_date] => 1994-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 21 [patent_no_of_words] => 4395 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/607/05607877.pdf [firstpage_image] =>[orig_patent_app_number] => 321013 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/321013
Projection-electrode fabrication method Oct 5, 1994 Issued
08/318408 METHOD OF MANUFACTURING FIELD EFFECT TRANSISTOR Oct 4, 1994 Abandoned
Array ( [id] => 3417408 [patent_doc_number] => 05434096 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-18 [patent_title] => 'Method to prevent silicide bubble in the VLSI process' [patent_app_type] => 1 [patent_app_number] => 8/318212 [patent_app_country] => US [patent_app_date] => 1994-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1610 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/434/05434096.pdf [firstpage_image] =>[orig_patent_app_number] => 318212 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/318212
Method to prevent silicide bubble in the VLSI process Oct 4, 1994 Issued
Array ( [id] => 3480437 [patent_doc_number] => 05405791 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-11 [patent_title] => 'Process for fabricating ULSI CMOS circuits using a single polysilicon gate layer and disposable spacers' [patent_app_type] => 1 [patent_app_number] => 8/317280 [patent_app_country] => US [patent_app_date] => 1994-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 3368 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/405/05405791.pdf [firstpage_image] =>[orig_patent_app_number] => 317280 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/317280
Process for fabricating ULSI CMOS circuits using a single polysilicon gate layer and disposable spacers Oct 3, 1994 Issued
Array ( [id] => 3514213 [patent_doc_number] => 05512516 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-30 [patent_title] => 'Contact structure for connecting an electrode to a semiconductor device and a method of forming the same' [patent_app_type] => 1 [patent_app_number] => 8/315576 [patent_app_country] => US [patent_app_date] => 1994-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5044 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/512/05512516.pdf [firstpage_image] =>[orig_patent_app_number] => 315576 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/315576
Contact structure for connecting an electrode to a semiconductor device and a method of forming the same Sep 29, 1994 Issued
Array ( [id] => 3453230 [patent_doc_number] => 05451545 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-19 [patent_title] => 'Process for forming stable local interconnect/active area silicide structure VLSI applications' [patent_app_type] => 1 [patent_app_number] => 8/309692 [patent_app_country] => US [patent_app_date] => 1994-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2356 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/451/05451545.pdf [firstpage_image] =>[orig_patent_app_number] => 309692 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/309692
Process for forming stable local interconnect/active area silicide structure VLSI applications Sep 20, 1994 Issued
Array ( [id] => 3412427 [patent_doc_number] => 05444017 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-22 [patent_title] => 'Method of making cBN semiconductor device having an ohmic electrode' [patent_app_type] => 1 [patent_app_number] => 8/305658 [patent_app_country] => US [patent_app_date] => 1994-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 1776 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/444/05444017.pdf [firstpage_image] =>[orig_patent_app_number] => 305658 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/305658
Method of making cBN semiconductor device having an ohmic electrode Sep 13, 1994 Issued
Array ( [id] => 3444340 [patent_doc_number] => 05420074 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-30 [patent_title] => 'Method for burying low resistance material in a contact hole' [patent_app_type] => 1 [patent_app_number] => 8/302398 [patent_app_country] => US [patent_app_date] => 1994-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 22 [patent_no_of_words] => 3526 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/420/05420074.pdf [firstpage_image] =>[orig_patent_app_number] => 302398 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/302398
Method for burying low resistance material in a contact hole Sep 7, 1994 Issued
08/300222 FORMATION OF ALUMINUM-ALLOY PATTERN Sep 5, 1994 Abandoned
Array ( [id] => 4354741 [patent_doc_number] => 06200871 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'High performance self-aligned silicide process for sub-half-micron semiconductor technologies' [patent_app_type] => 1 [patent_app_number] => 8/298018 [patent_app_country] => US [patent_app_date] => 1994-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4365 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/200/06200871.pdf [firstpage_image] =>[orig_patent_app_number] => 298018 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/298018
High performance self-aligned silicide process for sub-half-micron semiconductor technologies Aug 29, 1994 Issued
Array ( [id] => 3505116 [patent_doc_number] => 05514622 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-07 [patent_title] => 'Method for the formation of interconnects and landing pads having a thin, conductive film underlying the plug or an associated contact of via hole' [patent_app_type] => 1 [patent_app_number] => 8/297626 [patent_app_country] => US [patent_app_date] => 1994-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3220 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/514/05514622.pdf [firstpage_image] =>[orig_patent_app_number] => 297626 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/297626
Method for the formation of interconnects and landing pads having a thin, conductive film underlying the plug or an associated contact of via hole Aug 28, 1994 Issued
08/295514 WETTING LAYER SIDEWALLS TO PROMOTE COPPER REFLOW INTO GROOVES Aug 23, 1994 Abandoned
Array ( [id] => 3442178 [patent_doc_number] => 05466638 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-14 [patent_title] => 'Method of manufacturing a metal interconnect with high resistance to electromigration' [patent_app_type] => 1 [patent_app_number] => 8/292542 [patent_app_country] => US [patent_app_date] => 1994-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 4983 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/466/05466638.pdf [firstpage_image] =>[orig_patent_app_number] => 292542 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/292542
Method of manufacturing a metal interconnect with high resistance to electromigration Aug 15, 1994 Issued
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