Application number | Title of the application | Filing Date | Status |
---|
08/327588 | TAPER ETCHING WITHOUT RE-ENTRANCE PROFILE | Oct 23, 1994 | Abandoned |
Array
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[patent_issue_date] => 1997-04-15
[patent_title] => 'Method of manufacturing semiconductor device using a hagolen plasma treatment step'
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Array
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[patent_doc_number] => 05529953
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[patent_kind] => NA
[patent_issue_date] => 1996-06-25
[patent_title] => 'Method of forming studs and interconnects in a multi-layered semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/321896
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08/322546 | MANUFACTURE OF SEMICONDUCTOR DEVICE WITH SALICIDE ELECTRODE | Oct 12, 1994 | Abandoned |
08/322906 | DMOS TRANSISTOR WITH LOW ON-RESISTANCE AND METHOD OF FABRICATION | Oct 12, 1994 | Abandoned |
08/321560 | METHOD OF MAKING OHMIC CONTACT BETWEEN A THIN FILM POLYSILICON LAYER AND A SUBSEQUENTLY PROVIDED CONDUCTIVE LAYER AND INTEGRATED CIRCUITRY | Oct 11, 1994 | Abandoned |
08/319730 | FABRICATION PROCESS FOR SEMICONDUCTOR DEVICE | Oct 6, 1994 | Abandoned |
Array
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[patent_doc_number] => 05607877
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[patent_kind] => NA
[patent_issue_date] => 1997-03-04
[patent_title] => 'Projection-electrode fabrication method'
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[patent_app_number] => 8/321013
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08/318408 | METHOD OF MANUFACTURING FIELD EFFECT TRANSISTOR | Oct 4, 1994 | Abandoned |
Array
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[patent_doc_number] => 05434096
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[patent_kind] => NA
[patent_issue_date] => 1995-07-18
[patent_title] => 'Method to prevent silicide bubble in the VLSI process'
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[patent_app_number] => 8/318212
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Array
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[id] => 3480437
[patent_doc_number] => 05405791
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-11
[patent_title] => 'Process for fabricating ULSI CMOS circuits using a single polysilicon gate layer and disposable spacers'
[patent_app_type] => 1
[patent_app_number] => 8/317280
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Array
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[id] => 3514213
[patent_doc_number] => 05512516
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-30
[patent_title] => 'Contact structure for connecting an electrode to a semiconductor device and a method of forming the same'
[patent_app_type] => 1
[patent_app_number] => 8/315576
[patent_app_country] => US
[patent_app_date] => 1994-09-30
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[firstpage_image] =>[orig_patent_app_number] => 315576
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Array
(
[id] => 3453230
[patent_doc_number] => 05451545
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-09-19
[patent_title] => 'Process for forming stable local interconnect/active area silicide structure VLSI applications'
[patent_app_type] => 1
[patent_app_number] => 8/309692
[patent_app_country] => US
[patent_app_date] => 1994-09-21
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[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/05/451/05451545.pdf
[firstpage_image] =>[orig_patent_app_number] => 309692
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/309692 | Process for forming stable local interconnect/active area silicide structure VLSI applications | Sep 20, 1994 | Issued |
Array
(
[id] => 3412427
[patent_doc_number] => 05444017
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-22
[patent_title] => 'Method of making cBN semiconductor device having an ohmic electrode'
[patent_app_type] => 1
[patent_app_number] => 8/305658
[patent_app_country] => US
[patent_app_date] => 1994-09-14
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[patent_drawing_sheets_cnt] => 5
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[firstpage_image] =>[orig_patent_app_number] => 305658
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/305658 | Method of making cBN semiconductor device having an ohmic electrode | Sep 13, 1994 | Issued |
Array
(
[id] => 3444340
[patent_doc_number] => 05420074
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-30
[patent_title] => 'Method for burying low resistance material in a contact hole'
[patent_app_type] => 1
[patent_app_number] => 8/302398
[patent_app_country] => US
[patent_app_date] => 1994-09-08
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[pdf_file] => patents/05/420/05420074.pdf
[firstpage_image] =>[orig_patent_app_number] => 302398
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/302398 | Method for burying low resistance material in a contact hole | Sep 7, 1994 | Issued |
08/300222 | FORMATION OF ALUMINUM-ALLOY PATTERN | Sep 5, 1994 | Abandoned |
Array
(
[id] => 4354741
[patent_doc_number] => 06200871
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-03-13
[patent_title] => 'High performance self-aligned silicide process for sub-half-micron semiconductor technologies'
[patent_app_type] => 1
[patent_app_number] => 8/298018
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Array
(
[id] => 3505116
[patent_doc_number] => 05514622
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-07
[patent_title] => 'Method for the formation of interconnects and landing pads having a thin, conductive film underlying the plug or an associated contact of via hole'
[patent_app_type] => 1
[patent_app_number] => 8/297626
[patent_app_country] => US
[patent_app_date] => 1994-08-29
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/297626 | Method for the formation of interconnects and landing pads having a thin, conductive film underlying the plug or an associated contact of via hole | Aug 28, 1994 | Issued |
08/295514 | WETTING LAYER SIDEWALLS TO PROMOTE COPPER REFLOW INTO GROOVES | Aug 23, 1994 | Abandoned |
Array
(
[id] => 3442178
[patent_doc_number] => 05466638
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-14
[patent_title] => 'Method of manufacturing a metal interconnect with high resistance to electromigration'
[patent_app_type] => 1
[patent_app_number] => 8/292542
[patent_app_country] => US
[patent_app_date] => 1994-08-16
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/292542 | Method of manufacturing a metal interconnect with high resistance to electromigration | Aug 15, 1994 | Issued |