Search

Barbara J Bullock

Examiner (ID: 9881)

Most Active Art Unit
2901
Art Unit(s)
2900, 2912, 2901, 2902
Total Applications
4468
Issued Applications
4372
Pending Applications
0
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
08/290402 PROCESS FOR METALLIZATION OF AN INSULATOR LAYER Aug 14, 1994 Abandoned
Array ( [id] => 3109481 [patent_doc_number] => 05413963 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-09 [patent_title] => 'Method for depositing an insulating interlayer in a semiconductor metallurgy system' [patent_app_type] => 1 [patent_app_number] => 8/289648 [patent_app_country] => US [patent_app_date] => 1994-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2026 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/413/05413963.pdf [firstpage_image] =>[orig_patent_app_number] => 289648 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/289648
Method for depositing an insulating interlayer in a semiconductor metallurgy system Aug 11, 1994 Issued
Array ( [id] => 3487032 [patent_doc_number] => 05474943 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-12 [patent_title] => 'Method for fabricating a short channel trenched DMOS transistor' [patent_app_type] => 1 [patent_app_number] => 8/289358 [patent_app_country] => US [patent_app_date] => 1994-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 2747 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/474/05474943.pdf [firstpage_image] =>[orig_patent_app_number] => 289358 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/289358
Method for fabricating a short channel trenched DMOS transistor Aug 10, 1994 Issued
08/285972 PROCESS FOR FORMING CONTACTS IN SEMICONDUCTOR DEVICE Aug 3, 1994 Abandoned
Array ( [id] => 3656205 [patent_doc_number] => 05622893 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-22 [patent_title] => 'Method of forming conductive noble-metal-insulator-alloy barrier layer for high-dielectric-constant material electrodes' [patent_app_type] => 1 [patent_app_number] => 8/283454 [patent_app_country] => US [patent_app_date] => 1994-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 6717 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/622/05622893.pdf [firstpage_image] =>[orig_patent_app_number] => 283454 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/283454
Method of forming conductive noble-metal-insulator-alloy barrier layer for high-dielectric-constant material electrodes Jul 31, 1994 Issued
Array ( [id] => 4394839 [patent_doc_number] => 06297110 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Method of forming a contact in an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/282730 [patent_app_country] => US [patent_app_date] => 1994-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 4532 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297110.pdf [firstpage_image] =>[orig_patent_app_number] => 282730 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/282730
Method of forming a contact in an integrated circuit Jul 28, 1994 Issued
Array ( [id] => 3101990 [patent_doc_number] => 05447874 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-05 [patent_title] => 'Method for making a semiconductor device comprising a dual metal gate using a chemical mechanical polish' [patent_app_type] => 1 [patent_app_number] => 8/282360 [patent_app_country] => US [patent_app_date] => 1994-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2567 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/447/05447874.pdf [firstpage_image] =>[orig_patent_app_number] => 282360 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/282360
Method for making a semiconductor device comprising a dual metal gate using a chemical mechanical polish Jul 28, 1994 Issued
Array ( [id] => 3444763 [patent_doc_number] => 05397744 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-14 [patent_title] => 'Aluminum metallization method' [patent_app_type] => 1 [patent_app_number] => 8/283255 [patent_app_country] => US [patent_app_date] => 1994-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4843 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/397/05397744.pdf [firstpage_image] =>[orig_patent_app_number] => 283255 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/283255
Aluminum metallization method Jul 28, 1994 Issued
Array ( [id] => 3115150 [patent_doc_number] => 05449631 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-12 [patent_title] => 'Prevention of agglomeration and inversion in a semiconductor salicide process' [patent_app_type] => 1 [patent_app_number] => 8/282680 [patent_app_country] => US [patent_app_date] => 1994-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2339 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/449/05449631.pdf [firstpage_image] =>[orig_patent_app_number] => 282680 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/282680
Prevention of agglomeration and inversion in a semiconductor salicide process Jul 28, 1994 Issued
08/282144 CONDUCTIVE DIFFUSION BARRIER AND METHOD Jul 27, 1994 Abandoned
08/280450 METHOD OF PRODUCING SEMICONDUCTOR DEVICE Jul 25, 1994 Abandoned
08/275638 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE Jul 14, 1994 Abandoned
Array ( [id] => 3444435 [patent_doc_number] => 05397722 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-14 [patent_title] => 'Process for making self-aligned source/drain polysilicon or polysilicide contacts in field effect transistors' [patent_app_type] => 1 [patent_app_number] => 8/273534 [patent_app_country] => US [patent_app_date] => 1994-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3482 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/397/05397722.pdf [firstpage_image] =>[orig_patent_app_number] => 273534 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/273534
Process for making self-aligned source/drain polysilicon or polysilicide contacts in field effect transistors Jul 10, 1994 Issued
08/271233 PROCESS FOR PRODUCING HIGH PERFORMANCE BIPOLAR STRUCTURE Jul 5, 1994 Abandoned
Array ( [id] => 3472319 [patent_doc_number] => 05476814 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-19 [patent_title] => 'Method of manufacturing semiconductor device utilizing selective CVD method' [patent_app_type] => 1 [patent_app_number] => 8/267432 [patent_app_country] => US [patent_app_date] => 1994-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 78 [patent_no_of_words] => 6677 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/476/05476814.pdf [firstpage_image] =>[orig_patent_app_number] => 267432 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/267432
Method of manufacturing semiconductor device utilizing selective CVD method Jun 28, 1994 Issued
Array ( [id] => 3632983 [patent_doc_number] => 05610099 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-11 [patent_title] => 'Process for fabricating transistors using composite nitride structure' [patent_app_type] => 1 [patent_app_number] => 8/267278 [patent_app_country] => US [patent_app_date] => 1994-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 9651 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/610/05610099.pdf [firstpage_image] =>[orig_patent_app_number] => 267278 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/267278
Process for fabricating transistors using composite nitride structure Jun 27, 1994 Issued
Array ( [id] => 3423857 [patent_doc_number] => 05459101 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-17 [patent_title] => 'Method for fabricating a semiconductor device comprising a polycide structure' [patent_app_type] => 1 [patent_app_number] => 8/266218 [patent_app_country] => US [patent_app_date] => 1994-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4996 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/459/05459101.pdf [firstpage_image] =>[orig_patent_app_number] => 266218 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/266218
Method for fabricating a semiconductor device comprising a polycide structure Jun 26, 1994 Issued
Array ( [id] => 3412519 [patent_doc_number] => 05444024 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-22 [patent_title] => 'Method for low energy implantation of argon to control titanium silicide formation' [patent_app_type] => 1 [patent_app_number] => 8/258542 [patent_app_country] => US [patent_app_date] => 1994-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2851 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/444/05444024.pdf [firstpage_image] =>[orig_patent_app_number] => 258542 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/258542
Method for low energy implantation of argon to control titanium silicide formation Jun 9, 1994 Issued
Array ( [id] => 4353415 [patent_doc_number] => 06218223 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Process for producing electrode for semiconductor element and semiconductor device having the electrode' [patent_app_type] => 1 [patent_app_number] => 8/258370 [patent_app_country] => US [patent_app_date] => 1994-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 32 [patent_no_of_words] => 8086 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218223.pdf [firstpage_image] =>[orig_patent_app_number] => 258370 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/258370
Process for producing electrode for semiconductor element and semiconductor device having the electrode Jun 9, 1994 Issued
Array ( [id] => 3456056 [patent_doc_number] => 05401674 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-28 [patent_title] => 'Germanium implant for use with ultra-shallow junctions' [patent_app_type] => 1 [patent_app_number] => 8/258330 [patent_app_country] => US [patent_app_date] => 1994-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3471 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/401/05401674.pdf [firstpage_image] =>[orig_patent_app_number] => 258330 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/258330
Germanium implant for use with ultra-shallow junctions Jun 9, 1994 Issued
Menu