Search

Barbara J Bullock

Examiner (ID: 9881)

Most Active Art Unit
2901
Art Unit(s)
2900, 2912, 2901, 2902
Total Applications
4468
Issued Applications
4372
Pending Applications
0
Abandoned Applications
96

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3424999 [patent_doc_number] => 05422312 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-06 [patent_title] => 'Method for forming metal via' [patent_app_type] => 1 [patent_app_number] => 8/254122 [patent_app_country] => US [patent_app_date] => 1994-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 1613 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/422/05422312.pdf [firstpage_image] =>[orig_patent_app_number] => 254122 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/254122
Method for forming metal via Jun 5, 1994 Issued
Array ( [id] => 3410928 [patent_doc_number] => 05411902 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-02 [patent_title] => 'Process for improving gallium arsenide field effect transistor performance using an aluminum arsenide or an aluminum gallium arsenide buffer layer' [patent_app_type] => 1 [patent_app_number] => 8/254722 [patent_app_country] => US [patent_app_date] => 1994-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1437 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/411/05411902.pdf [firstpage_image] =>[orig_patent_app_number] => 254722 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/254722
Process for improving gallium arsenide field effect transistor performance using an aluminum arsenide or an aluminum gallium arsenide buffer layer Jun 5, 1994 Issued
08/254668 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE USING SOI (SEMICONDUCTOR ON INSULATOR) SUBSTRATE Jun 5, 1994 Abandoned
Array ( [id] => 4287262 [patent_doc_number] => 06268290 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Method of forming wirings' [patent_app_type] => 1 [patent_app_number] => 8/250332 [patent_app_country] => US [patent_app_date] => 1994-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 39 [patent_no_of_words] => 4855 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268290.pdf [firstpage_image] =>[orig_patent_app_number] => 250332 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/250332
Method of forming wirings May 26, 1994 Issued
Array ( [id] => 3453091 [patent_doc_number] => 05451535 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-19 [patent_title] => 'Method for manufacturing a memory cell' [patent_app_type] => 1 [patent_app_number] => 8/247170 [patent_app_country] => US [patent_app_date] => 1994-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4145 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 396 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/451/05451535.pdf [firstpage_image] =>[orig_patent_app_number] => 247170 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/247170
Method for manufacturing a memory cell May 19, 1994 Issued
Array ( [id] => 3113111 [patent_doc_number] => 05409853 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-25 [patent_title] => 'Process of making silicided contacts for semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 8/246532 [patent_app_country] => US [patent_app_date] => 1994-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2764 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/409/05409853.pdf [firstpage_image] =>[orig_patent_app_number] => 246532 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/246532
Process of making silicided contacts for semiconductor devices May 19, 1994 Issued
Array ( [id] => 3450138 [patent_doc_number] => 05385849 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-31 [patent_title] => 'Process of fabricating solid-state image pick-up device free from crystal defects in active region' [patent_app_type] => 1 [patent_app_number] => 8/242954 [patent_app_country] => US [patent_app_date] => 1994-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 3298 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 334 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/385/05385849.pdf [firstpage_image] =>[orig_patent_app_number] => 242954 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/242954
Process of fabricating solid-state image pick-up device free from crystal defects in active region May 15, 1994 Issued
Array ( [id] => 3107065 [patent_doc_number] => 05407848 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-18 [patent_title] => 'Method for forming a gate electrode having a polycide structure' [patent_app_type] => 1 [patent_app_number] => 8/242474 [patent_app_country] => US [patent_app_date] => 1994-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1084 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/407/05407848.pdf [firstpage_image] =>[orig_patent_app_number] => 242474 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/242474
Method for forming a gate electrode having a polycide structure May 12, 1994 Issued
Array ( [id] => 3102028 [patent_doc_number] => 05447875 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-05 [patent_title] => 'Self-aligned silicided gate process' [patent_app_type] => 1 [patent_app_number] => 8/240799 [patent_app_country] => US [patent_app_date] => 1994-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 2606 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/447/05447875.pdf [firstpage_image] =>[orig_patent_app_number] => 240799 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/240799
Self-aligned silicided gate process May 10, 1994 Issued
Array ( [id] => 2993280 [patent_doc_number] => 05366911 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-22 [patent_title] => 'VLSI process with global planarization' [patent_app_type] => 1 [patent_app_number] => 8/240572 [patent_app_country] => US [patent_app_date] => 1994-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2773 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 362 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/366/05366911.pdf [firstpage_image] =>[orig_patent_app_number] => 240572 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/240572
VLSI process with global planarization May 10, 1994 Issued
Array ( [id] => 3580602 [patent_doc_number] => 05498558 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-12 [patent_title] => 'Integrated circuit structure having floating electrode with discontinuous phase of metal silicide formed on a surface thereof and process for making same' [patent_app_type] => 1 [patent_app_number] => 8/239422 [patent_app_country] => US [patent_app_date] => 1994-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3862 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/498/05498558.pdf [firstpage_image] =>[orig_patent_app_number] => 239422 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/239422
Integrated circuit structure having floating electrode with discontinuous phase of metal silicide formed on a surface thereof and process for making same May 5, 1994 Issued
Array ( [id] => 3071690 [patent_doc_number] => 05364817 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-15 [patent_title] => 'Tungsten-plug process' [patent_app_type] => 1 [patent_app_number] => 8/238664 [patent_app_country] => US [patent_app_date] => 1994-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 1911 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/364/05364817.pdf [firstpage_image] =>[orig_patent_app_number] => 238664 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/238664
Tungsten-plug process May 4, 1994 Issued
Array ( [id] => 3424984 [patent_doc_number] => 05422311 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-06 [patent_title] => 'Method for manufacturing a conductor layer in a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/236860 [patent_app_country] => US [patent_app_date] => 1994-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 1987 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/422/05422311.pdf [firstpage_image] =>[orig_patent_app_number] => 236860 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/236860
Method for manufacturing a conductor layer in a semiconductor device May 1, 1994 Issued
Array ( [id] => 3459065 [patent_doc_number] => 05441914 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-15 [patent_title] => 'Method of forming conductive interconnect structure' [patent_app_type] => 1 [patent_app_number] => 8/236076 [patent_app_country] => US [patent_app_date] => 1994-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3042 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/441/05441914.pdf [firstpage_image] =>[orig_patent_app_number] => 236076 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/236076
Method of forming conductive interconnect structure May 1, 1994 Issued
Array ( [id] => 3459091 [patent_doc_number] => 05441916 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-15 [patent_title] => 'Method of manufacturing semiconductor device comprising interconnection' [patent_app_type] => 1 [patent_app_number] => 8/234806 [patent_app_country] => US [patent_app_date] => 1994-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 3746 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/441/05441916.pdf [firstpage_image] =>[orig_patent_app_number] => 234806 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/234806
Method of manufacturing semiconductor device comprising interconnection Apr 27, 1994 Issued
Array ( [id] => 3122078 [patent_doc_number] => 05384273 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-24 [patent_title] => 'Method of making a semiconductor device having a short gate length' [patent_app_type] => 1 [patent_app_number] => 8/233290 [patent_app_country] => US [patent_app_date] => 1994-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 1838 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/384/05384273.pdf [firstpage_image] =>[orig_patent_app_number] => 233290 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/233290
Method of making a semiconductor device having a short gate length Apr 25, 1994 Issued
Array ( [id] => 3480656 [patent_doc_number] => 05405806 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-11 [patent_title] => 'Method for forming a metal silicide interconnect in an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/219328 [patent_app_country] => US [patent_app_date] => 1994-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 22 [patent_no_of_words] => 5187 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 355 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/405/05405806.pdf [firstpage_image] =>[orig_patent_app_number] => 219328 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/219328
Method for forming a metal silicide interconnect in an integrated circuit Mar 28, 1994 Issued
Array ( [id] => 3450390 [patent_doc_number] => 05385867 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-31 [patent_title] => 'Method for forming a multi-layer metallic wiring structure' [patent_app_type] => 1 [patent_app_number] => 8/216968 [patent_app_country] => US [patent_app_date] => 1994-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 52 [patent_no_of_words] => 8497 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/385/05385867.pdf [firstpage_image] =>[orig_patent_app_number] => 216968 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/216968
Method for forming a multi-layer metallic wiring structure Mar 23, 1994 Issued
Array ( [id] => 3459078 [patent_doc_number] => 05441915 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-15 [patent_title] => 'Process of fabrication planarized metallurgy structure for a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/214852 [patent_app_country] => US [patent_app_date] => 1994-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 2865 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/441/05441915.pdf [firstpage_image] =>[orig_patent_app_number] => 214852 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/214852
Process of fabrication planarized metallurgy structure for a semiconductor device Mar 17, 1994 Issued
08/210071 CONTACTS FOR SEMICONDUCTOR DEVICES Mar 16, 1994 Abandoned
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