Barbara J Bullock

Array ( [id] => 3446131 [patent_doc_number] => 05387529 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-07 [patent_title] => 'Production method of a MESFET semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/152963 [patent_app_country] => US [patent_app_date] => 1993-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 42 [patent_no_of_words] => 5283 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/387/05387529.pdf [firstpage_image] =>[orig_patent_app_number] => 152963 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3415613 [patent_doc_number] => 05393703 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-28 [patent_title] => 'Process for forming a conductive layer for semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 8/150900 [patent_app_country] => US [patent_app_date] => 1993-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2785 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/393/05393703.pdf [firstpage_image] =>[orig_patent_app_number] => 150900 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3489493 [patent_doc_number] => 05439847 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-08 [patent_title] => 'Integrated circuit fabrication with a raised feature as mask' [patent_app_type] => 1 [patent_app_number] => 8/147368 [patent_app_country] => US [patent_app_date] => 1993-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1278 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/439/05439847.pdf [firstpage_image] =>[orig_patent_app_number] => 147368 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3487056 [patent_doc_number] => 05474945 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-12 [patent_title] => 'Method for forming semiconductor device comprising metal oxide' [patent_app_type] => 1 [patent_app_number] => 8/147580 [patent_app_country] => US [patent_app_date] => 1993-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 40 [patent_no_of_words] => 12500 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/474/05474945.pdf [firstpage_image] =>[orig_patent_app_number] => 147580 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3056936 [patent_doc_number] => 05338701 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-16 [patent_title] => 'Method for fabrication of w-polycide-to-poly capacitors with high linearity' [patent_app_type] => 1 [patent_app_number] => 8/145154 [patent_app_country] => US [patent_app_date] => 1993-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3958 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/338/05338701.pdf [firstpage_image] =>[orig_patent_app_number] => 145154 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3071442 [patent_doc_number] => 05364804 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-15 [patent_title] => 'Nitride cap sidewall oxide protection from BOE etch' [patent_app_type] => 1 [patent_app_number] => 8/145160 [patent_app_country] => US [patent_app_date] => 1993-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2068 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/364/05364804.pdf [firstpage_image] =>[orig_patent_app_number] => 145160 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4405384 [patent_doc_number] => 06271137 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Method of producing an aluminum stacked contact/via for multilayer' [patent_app_type] => 1 [patent_app_number] => 8/146823 [patent_app_country] => US [patent_app_date] => 1993-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 8 [patent_no_of_words] => 3321 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 407 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271137.pdf [firstpage_image] =>[orig_patent_app_number] => 146823 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3460960 [patent_doc_number] => 05468669 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-21 [patent_title] => 'Integrated circuit fabrication' [patent_app_type] => 1 [patent_app_number] => 8/145272 [patent_app_country] => US [patent_app_date] => 1993-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1015 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/468/05468669.pdf [firstpage_image] =>[orig_patent_app_number] => 145272 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3117548 [patent_doc_number] => 05380680 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-10 [patent_title] => 'Method for forming a metal contact of a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/138694 [patent_app_country] => US [patent_app_date] => 1993-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 913 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/380/05380680.pdf [firstpage_image] =>[orig_patent_app_number] => 138694 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3460132 [patent_doc_number] => 05391520 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-21 [patent_title] => 'Method for forming local interconnect for integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/139268 [patent_app_country] => US [patent_app_date] => 1993-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1942 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/391/05391520.pdf [firstpage_image] =>[orig_patent_app_number] => 139268 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3611610 [patent_doc_number] => 05565382 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-15 [patent_title] => 'Process for forming tungsten silicide on semiconductor wafer using dichlorosilane gas' [patent_app_type] => 1 [patent_app_number] => 8/135202 [patent_app_country] => US [patent_app_date] => 1993-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 5401 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/565/05565382.pdf [firstpage_image] =>[orig_patent_app_number] => 135202 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3049763 [patent_doc_number] => 05306665 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-26 [patent_title] => 'Manufacturing a wiring for a semiconductor device by a forwardly tapered stack of two conductor films' [patent_app_type] => 1 [patent_app_number] => 8/132345 [patent_app_country] => US [patent_app_date] => 1993-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2490 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/306/05306665.pdf [firstpage_image] =>[orig_patent_app_number] => 132345 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3112382 [patent_doc_number] => 05395799 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-07 [patent_title] => 'Method of fabricating semiconductor devices having electrodes comprising layers of doped tungsten disilicide' [patent_app_type] => 1 [patent_app_number] => 8/131508 [patent_app_country] => US [patent_app_date] => 1993-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3390 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/395/05395799.pdf [firstpage_image] =>[orig_patent_app_number] => 131508 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3581720 [patent_doc_number] => 05580825 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-03 [patent_title] => 'Process for making multilevel interconnections of electronic components' [patent_app_type] => 1 [patent_app_number] => 8/124282 [patent_app_country] => US [patent_app_date] => 1993-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 40 [patent_no_of_words] => 10620 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/580/05580825.pdf [firstpage_image] =>[orig_patent_app_number] => 124282 [rel_patent_id] =>[rel_patent_doc_number] =>)