Search

Belur V. Keshavan

Examiner (ID: 2641)

Most Active Art Unit
2825
Art Unit(s)
2825, 2823
Total Applications
284
Issued Applications
267
Pending Applications
6
Abandoned Applications
11

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4401453 [patent_doc_number] => 06297544 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/462840 [patent_app_country] => US [patent_app_date] => 2000-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6585 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297544.pdf [firstpage_image] =>[orig_patent_app_number] => 462840 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/462840
Semiconductor device and method for manufacturing the same Jan 13, 2000 Issued
Array ( [id] => 1453537 [patent_doc_number] => 06461929 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Method for the fine tuning of a passive electronic component' [patent_app_type] => B1 [patent_app_number] => 09/479640 [patent_app_country] => US [patent_app_date] => 2000-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1958 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/461/06461929.pdf [firstpage_image] =>[orig_patent_app_number] => 09479640 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/479640
Method for the fine tuning of a passive electronic component Jan 6, 2000 Issued
Array ( [id] => 1514439 [patent_doc_number] => 06420207 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Semiconductor package and enhanced FBG manufacturing' [patent_app_type] => B1 [patent_app_number] => 09/477350 [patent_app_country] => US [patent_app_date] => 2000-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 3604 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/420/06420207.pdf [firstpage_image] =>[orig_patent_app_number] => 09477350 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/477350
Semiconductor package and enhanced FBG manufacturing Jan 3, 2000 Issued
Array ( [id] => 1440013 [patent_doc_number] => 06495409 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'MOS transistor having aluminum nitride gate structure and method of manufacturing same' [patent_app_type] => B1 [patent_app_number] => 09/472331 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2103 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/495/06495409.pdf [firstpage_image] =>[orig_patent_app_number] => 09472331 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/472331
MOS transistor having aluminum nitride gate structure and method of manufacturing same Dec 22, 1999 Issued
Array ( [id] => 4358265 [patent_doc_number] => 06255173 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Method of forming gate electrode with titanium polycide structure' [patent_app_type] => 1 [patent_app_number] => 9/466741 [patent_app_country] => US [patent_app_date] => 1999-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 1750 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255173.pdf [firstpage_image] =>[orig_patent_app_number] => 466741 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/466741
Method of forming gate electrode with titanium polycide structure Dec 16, 1999 Issued
Array ( [id] => 1446598 [patent_doc_number] => 06368936 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Method for forming a semiconductor integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/444430 [patent_app_country] => US [patent_app_date] => 1999-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 31 [patent_no_of_words] => 2473 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/368/06368936.pdf [firstpage_image] =>[orig_patent_app_number] => 09444430 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/444430
Method for forming a semiconductor integrated circuit Nov 18, 1999 Issued
Array ( [id] => 4329067 [patent_doc_number] => 06313000 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Process for formation of vertically isolated bipolar transistor device' [patent_app_type] => 1 [patent_app_number] => 9/442810 [patent_app_country] => US [patent_app_date] => 1999-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 2594 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/313/06313000.pdf [firstpage_image] =>[orig_patent_app_number] => 442810 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/442810
Process for formation of vertically isolated bipolar transistor device Nov 17, 1999 Issued
Array ( [id] => 1361937 [patent_doc_number] => 06569757 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Methods for forming co-axial interconnect lines in a CMOS process for high speed applications' [patent_app_type] => B1 [patent_app_number] => 09/429540 [patent_app_country] => US [patent_app_date] => 1999-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 4181 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/569/06569757.pdf [firstpage_image] =>[orig_patent_app_number] => 09429540 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/429540
Methods for forming co-axial interconnect lines in a CMOS process for high speed applications Oct 27, 1999 Issued
Array ( [id] => 4324558 [patent_doc_number] => 06329235 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Method of performing a pocket implantation on a MOS transistor of a memory cell of a DRAM' [patent_app_type] => 1 [patent_app_number] => 9/421259 [patent_app_country] => US [patent_app_date] => 1999-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2579 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329235.pdf [firstpage_image] =>[orig_patent_app_number] => 421259 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/421259
Method of performing a pocket implantation on a MOS transistor of a memory cell of a DRAM Oct 19, 1999 Issued
Array ( [id] => 4381515 [patent_doc_number] => 06277727 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Method of forming a landing pad on a semiconductor wafer' [patent_app_type] => 1 [patent_app_number] => 9/421247 [patent_app_country] => US [patent_app_date] => 1999-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 2271 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/277/06277727.pdf [firstpage_image] =>[orig_patent_app_number] => 421247 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/421247
Method of forming a landing pad on a semiconductor wafer Oct 19, 1999 Issued
Array ( [id] => 4270933 [patent_doc_number] => 06323078 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Method of forming metal oxide metal capacitors using multi-step rapid thermal process and a device formed thereby' [patent_app_type] => 1 [patent_app_number] => 9/418106 [patent_app_country] => US [patent_app_date] => 1999-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2997 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323078.pdf [firstpage_image] =>[orig_patent_app_number] => 418106 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/418106
Method of forming metal oxide metal capacitors using multi-step rapid thermal process and a device formed thereby Oct 13, 1999 Issued
Array ( [id] => 4408499 [patent_doc_number] => 06300215 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Methods of forming integrated circuit capacitors having composite titanium oxide and tantalum pentoxide dielectric layers therein' [patent_app_type] => 1 [patent_app_number] => 9/417859 [patent_app_country] => US [patent_app_date] => 1999-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2861 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/300/06300215.pdf [firstpage_image] =>[orig_patent_app_number] => 417859 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/417859
Methods of forming integrated circuit capacitors having composite titanium oxide and tantalum pentoxide dielectric layers therein Oct 13, 1999 Issued
Array ( [id] => 4404864 [patent_doc_number] => 06271099 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Method for forming a capacitor of a DRAM cell' [patent_app_type] => 1 [patent_app_number] => 9/406728 [patent_app_country] => US [patent_app_date] => 1999-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3120 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271099.pdf [firstpage_image] =>[orig_patent_app_number] => 406728 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/406728
Method for forming a capacitor of a DRAM cell Sep 27, 1999 Issued
Array ( [id] => 4266541 [patent_doc_number] => 06306695 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Modified source side inserted anti-type diffusion ESD protection device' [patent_app_type] => 1 [patent_app_number] => 9/407110 [patent_app_country] => US [patent_app_date] => 1999-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3470 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/306/06306695.pdf [firstpage_image] =>[orig_patent_app_number] => 407110 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/407110
Modified source side inserted anti-type diffusion ESD protection device Sep 26, 1999 Issued
Array ( [id] => 1433549 [patent_doc_number] => 06340839 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Hybrid integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/401128 [patent_app_country] => US [patent_app_date] => 1999-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4927 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/340/06340839.pdf [firstpage_image] =>[orig_patent_app_number] => 09401128 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/401128
Hybrid integrated circuit Sep 21, 1999 Issued
Array ( [id] => 4336233 [patent_doc_number] => 06333222 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => 1 [patent_app_number] => 9/399369 [patent_app_country] => US [patent_app_date] => 1999-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 26 [patent_no_of_words] => 8197 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/333/06333222.pdf [firstpage_image] =>[orig_patent_app_number] => 399369 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/399369
Semiconductor device and manufacturing method thereof Sep 19, 1999 Issued
Array ( [id] => 4131695 [patent_doc_number] => 06121128 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Method for making borderless wordline for DRAM cell' [patent_app_type] => 1 [patent_app_number] => 9/398659 [patent_app_country] => US [patent_app_date] => 1999-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 3334 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121128.pdf [firstpage_image] =>[orig_patent_app_number] => 398659 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/398659
Method for making borderless wordline for DRAM cell Sep 16, 1999 Issued
Array ( [id] => 4354770 [patent_doc_number] => 06200873 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Production method for a trench capacitor with an insulation collar' [patent_app_type] => 1 [patent_app_number] => 9/395226 [patent_app_country] => US [patent_app_date] => 1999-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 31 [patent_no_of_words] => 11043 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/200/06200873.pdf [firstpage_image] =>[orig_patent_app_number] => 395226 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/395226
Production method for a trench capacitor with an insulation collar Sep 12, 1999 Issued
Array ( [id] => 4169026 [patent_doc_number] => 06140181 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Memory using insulator traps' [patent_app_type] => 1 [patent_app_number] => 9/394109 [patent_app_country] => US [patent_app_date] => 1999-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4252 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/140/06140181.pdf [firstpage_image] =>[orig_patent_app_number] => 394109 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/394109
Memory using insulator traps Sep 9, 1999 Issued
Array ( [id] => 4324808 [patent_doc_number] => 06329252 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Method of forming self-aligned contacts' [patent_app_type] => 1 [patent_app_number] => 9/393580 [patent_app_country] => US [patent_app_date] => 1999-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 1960 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329252.pdf [firstpage_image] =>[orig_patent_app_number] => 393580 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/393580
Method of forming self-aligned contacts Sep 8, 1999 Issued
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