Search

Belur V. Keshavan

Examiner (ID: 2641)

Most Active Art Unit
2825
Art Unit(s)
2825, 2823
Total Applications
284
Issued Applications
267
Pending Applications
6
Abandoned Applications
11

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4188183 [patent_doc_number] => 06153469 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Method of fabricating cell of flash memory device' [patent_app_type] => 1 [patent_app_number] => 9/352448 [patent_app_country] => US [patent_app_date] => 1999-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 35 [patent_no_of_words] => 5745 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153469.pdf [firstpage_image] =>[orig_patent_app_number] => 352448 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/352448
Method of fabricating cell of flash memory device Jul 12, 1999 Issued
Array ( [id] => 4289016 [patent_doc_number] => 06235542 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Ferroelectric memory device and method for fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/346089 [patent_app_country] => US [patent_app_date] => 1999-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2331 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/235/06235542.pdf [firstpage_image] =>[orig_patent_app_number] => 346089 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/346089
Ferroelectric memory device and method for fabricating the same Jun 30, 1999 Issued
Array ( [id] => 4194959 [patent_doc_number] => 06153913 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Electrostatic discharge protection circuit' [patent_app_type] => 1 [patent_app_number] => 9/345674 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2580 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153913.pdf [firstpage_image] =>[orig_patent_app_number] => 345674 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/345674
Electrostatic discharge protection circuit Jun 29, 1999 Issued
Array ( [id] => 4408148 [patent_doc_number] => 06265260 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Method for making an integrated circuit capacitor including tantalum pentoxide' [patent_app_type] => 1 [patent_app_number] => 9/345556 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2032 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265260.pdf [firstpage_image] =>[orig_patent_app_number] => 345556 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/345556
Method for making an integrated circuit capacitor including tantalum pentoxide Jun 29, 1999 Issued
Array ( [id] => 6342778 [patent_doc_number] => 20020034853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-21 [patent_title] => 'STRUCTURE AND PROCESS FLOW FOR FABRICATION OF DUAL GATE FLOATING BODY INTEGRATED MOS TRANSISTORS' [patent_app_type] => new [patent_app_number] => 09/342022 [patent_app_country] => US [patent_app_date] => 1999-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3588 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20020034853.pdf [firstpage_image] =>[orig_patent_app_number] => 09342022 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/342022
Structure and process flow for fabrication of dual gate floating body integrated MOS transistors Jun 27, 1999 Issued
Array ( [id] => 4191234 [patent_doc_number] => 06130126 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Self-planarizing DRAM chip avoids edge flaking' [patent_app_type] => 1 [patent_app_number] => 9/339728 [patent_app_country] => US [patent_app_date] => 1999-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 2203 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130126.pdf [firstpage_image] =>[orig_patent_app_number] => 339728 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/339728
Self-planarizing DRAM chip avoids edge flaking Jun 23, 1999 Issued
Array ( [id] => 4089565 [patent_doc_number] => 06163056 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Semiconductor device having electrostatic discharge' [patent_app_type] => 1 [patent_app_number] => 9/336750 [patent_app_country] => US [patent_app_date] => 1999-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5194 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163056.pdf [firstpage_image] =>[orig_patent_app_number] => 336750 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/336750
Semiconductor device having electrostatic discharge Jun 20, 1999 Issued
Array ( [id] => 4406819 [patent_doc_number] => 06238949 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Method and apparatus for forming a plastic chip on chip package module' [patent_app_type] => 1 [patent_app_number] => 9/336037 [patent_app_country] => US [patent_app_date] => 1999-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3455 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/238/06238949.pdf [firstpage_image] =>[orig_patent_app_number] => 336037 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/336037
Method and apparatus for forming a plastic chip on chip package module Jun 17, 1999 Issued
Array ( [id] => 4387455 [patent_doc_number] => 06294822 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Spheric semiconductor device, method for manufacturing the same, and spheric semiconductor device material' [patent_app_type] => 1 [patent_app_number] => 9/297207 [patent_app_country] => US [patent_app_date] => 1999-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 11394 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/294/06294822.pdf [firstpage_image] =>[orig_patent_app_number] => 297207 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/297207
Spheric semiconductor device, method for manufacturing the same, and spheric semiconductor device material Jun 9, 1999 Issued
Array ( [id] => 1576314 [patent_doc_number] => 06469351 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Electrostatic breakdown prevention circuit for semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/323505 [patent_app_country] => US [patent_app_date] => 1999-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 1526 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/469/06469351.pdf [firstpage_image] =>[orig_patent_app_number] => 09323505 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/323505
Electrostatic breakdown prevention circuit for semiconductor device May 31, 1999 Issued
Array ( [id] => 4254146 [patent_doc_number] => 06222207 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Diffusion barrier for increased mirror reflectivity in reflective solderable contacts on high power LED chip' [patent_app_type] => 1 [patent_app_number] => 9/317647 [patent_app_country] => US [patent_app_date] => 1999-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4736 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222207.pdf [firstpage_image] =>[orig_patent_app_number] => 317647 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/317647
Diffusion barrier for increased mirror reflectivity in reflective solderable contacts on high power LED chip May 23, 1999 Issued
Array ( [id] => 4414457 [patent_doc_number] => 06229203 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Semiconductor interconnect structure for high temperature applications' [patent_app_type] => 1 [patent_app_number] => 9/312537 [patent_app_country] => US [patent_app_date] => 1999-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2646 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229203.pdf [firstpage_image] =>[orig_patent_app_number] => 312537 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/312537
Semiconductor interconnect structure for high temperature applications May 23, 1999 Issued
Array ( [id] => 4356793 [patent_doc_number] => 06190944 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Stacked package for semiconductor device and fabrication method thereof, and apparatus for making the stacked package' [patent_app_type] => 1 [patent_app_number] => 9/314010 [patent_app_country] => US [patent_app_date] => 1999-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 4752 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/190/06190944.pdf [firstpage_image] =>[orig_patent_app_number] => 314010 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314010
Stacked package for semiconductor device and fabrication method thereof, and apparatus for making the stacked package May 18, 1999 Issued
Array ( [id] => 4084800 [patent_doc_number] => 06025245 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Method of forming a trench capacitor with a sacrificial silicon nitrate sidewall' [patent_app_type] => 1 [patent_app_number] => 9/313668 [patent_app_country] => US [patent_app_date] => 1999-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2102 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/025/06025245.pdf [firstpage_image] =>[orig_patent_app_number] => 313668 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/313668
Method of forming a trench capacitor with a sacrificial silicon nitrate sidewall May 17, 1999 Issued
Array ( [id] => 1486732 [patent_doc_number] => 06365937 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Electrostatic discharge protection device having a graded junction' [patent_app_type] => B1 [patent_app_number] => 09/310538 [patent_app_country] => US [patent_app_date] => 1999-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 5589 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/365/06365937.pdf [firstpage_image] =>[orig_patent_app_number] => 09310538 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/310538
Electrostatic discharge protection device having a graded junction May 11, 1999 Issued
Array ( [id] => 4419535 [patent_doc_number] => 06177323 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Method to form MOSFET with an elevated source/drain for PMOSFET' [patent_app_type] => 1 [patent_app_number] => 9/303143 [patent_app_country] => US [patent_app_date] => 1999-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2747 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/177/06177323.pdf [firstpage_image] =>[orig_patent_app_number] => 303143 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/303143
Method to form MOSFET with an elevated source/drain for PMOSFET Apr 29, 1999 Issued
Array ( [id] => 4177605 [patent_doc_number] => 06037208 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Method for forming a deep trench capacitor of a DRAM cell' [patent_app_type] => 1 [patent_app_number] => 9/298868 [patent_app_country] => US [patent_app_date] => 1999-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2952 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/037/06037208.pdf [firstpage_image] =>[orig_patent_app_number] => 298868 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/298868
Method for forming a deep trench capacitor of a DRAM cell Apr 25, 1999 Issued
Array ( [id] => 4162729 [patent_doc_number] => 06157062 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Integrating dual supply voltage by removing the drain extender implant from the high voltage device' [patent_app_type] => 1 [patent_app_number] => 9/287227 [patent_app_country] => US [patent_app_date] => 1999-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1935 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157062.pdf [firstpage_image] =>[orig_patent_app_number] => 287227 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/287227
Integrating dual supply voltage by removing the drain extender implant from the high voltage device Apr 5, 1999 Issued
Array ( [id] => 4357370 [patent_doc_number] => 06174795 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Method for preventing tungsten contact plug loss after a backside pressure fault' [patent_app_type] => 1 [patent_app_number] => 9/282993 [patent_app_country] => US [patent_app_date] => 1999-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3453 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/174/06174795.pdf [firstpage_image] =>[orig_patent_app_number] => 282993 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/282993
Method for preventing tungsten contact plug loss after a backside pressure fault Mar 30, 1999 Issued
Array ( [id] => 4405860 [patent_doc_number] => 06232221 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Borderless vias' [patent_app_type] => 1 [patent_app_number] => 9/260001 [patent_app_country] => US [patent_app_date] => 1999-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4253 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232221.pdf [firstpage_image] =>[orig_patent_app_number] => 260001 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/260001
Borderless vias Mar 1, 1999 Issued
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