
Belur V. Keshavan
Examiner (ID: 2641)
| Most Active Art Unit | 2825 |
| Art Unit(s) | 2825, 2823 |
| Total Applications | 284 |
| Issued Applications | 267 |
| Pending Applications | 6 |
| Abandoned Applications | 11 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4188183
[patent_doc_number] => 06153469
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-28
[patent_title] => 'Method of fabricating cell of flash memory device'
[patent_app_type] => 1
[patent_app_number] => 9/352448
[patent_app_country] => US
[patent_app_date] => 1999-07-13
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/153/06153469.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/352448 | Method of fabricating cell of flash memory device | Jul 12, 1999 | Issued |
Array
(
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[patent_doc_number] => 06235542
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[patent_kind] => NA
[patent_issue_date] => 2001-05-22
[patent_title] => 'Ferroelectric memory device and method for fabricating the same'
[patent_app_type] => 1
[patent_app_number] => 9/346089
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[patent_app_date] => 1999-07-01
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/346089 | Ferroelectric memory device and method for fabricating the same | Jun 30, 1999 | Issued |
Array
(
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[patent_doc_number] => 06153913
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[patent_issue_date] => 2000-11-28
[patent_title] => 'Electrostatic discharge protection circuit'
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[patent_app_number] => 9/345674
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[patent_app_date] => 1999-06-30
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Array
(
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[patent_doc_number] => 06265260
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[patent_kind] => NA
[patent_issue_date] => 2001-07-24
[patent_title] => 'Method for making an integrated circuit capacitor including tantalum pentoxide'
[patent_app_type] => 1
[patent_app_number] => 9/345556
[patent_app_country] => US
[patent_app_date] => 1999-06-30
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[firstpage_image] =>[orig_patent_app_number] => 345556
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Array
(
[id] => 6342778
[patent_doc_number] => 20020034853
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-03-21
[patent_title] => 'STRUCTURE AND PROCESS FLOW FOR FABRICATION OF DUAL GATE FLOATING BODY INTEGRATED MOS TRANSISTORS'
[patent_app_type] => new
[patent_app_number] => 09/342022
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[patent_app_date] => 1999-06-28
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[pdf_file] => publications/A1/0034/20020034853.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/342022 | Structure and process flow for fabrication of dual gate floating body integrated MOS transistors | Jun 27, 1999 | Issued |
Array
(
[id] => 4191234
[patent_doc_number] => 06130126
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[patent_issue_date] => 2000-10-10
[patent_title] => 'Self-planarizing DRAM chip avoids edge flaking'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/339728 | Self-planarizing DRAM chip avoids edge flaking | Jun 23, 1999 | Issued |
Array
(
[id] => 4089565
[patent_doc_number] => 06163056
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[patent_issue_date] => 2000-12-19
[patent_title] => 'Semiconductor device having electrostatic discharge'
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[patent_app_date] => 1999-06-21
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[firstpage_image] =>[orig_patent_app_number] => 336750
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/336750 | Semiconductor device having electrostatic discharge | Jun 20, 1999 | Issued |
Array
(
[id] => 4406819
[patent_doc_number] => 06238949
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[patent_kind] => NA
[patent_issue_date] => 2001-05-29
[patent_title] => 'Method and apparatus for forming a plastic chip on chip package module'
[patent_app_type] => 1
[patent_app_number] => 9/336037
[patent_app_country] => US
[patent_app_date] => 1999-06-18
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[pdf_file] => patents/06/238/06238949.pdf
[firstpage_image] =>[orig_patent_app_number] => 336037
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/336037 | Method and apparatus for forming a plastic chip on chip package module | Jun 17, 1999 | Issued |
Array
(
[id] => 4387455
[patent_doc_number] => 06294822
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-25
[patent_title] => 'Spheric semiconductor device, method for manufacturing the same, and spheric semiconductor device material'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/297207 | Spheric semiconductor device, method for manufacturing the same, and spheric semiconductor device material | Jun 9, 1999 | Issued |
Array
(
[id] => 1576314
[patent_doc_number] => 06469351
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[patent_issue_date] => 2002-10-22
[patent_title] => 'Electrostatic breakdown prevention circuit for semiconductor device'
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[patent_app_number] => 09/323505
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/323505 | Electrostatic breakdown prevention circuit for semiconductor device | May 31, 1999 | Issued |
Array
(
[id] => 4254146
[patent_doc_number] => 06222207
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-24
[patent_title] => 'Diffusion barrier for increased mirror reflectivity in reflective solderable contacts on high power LED chip'
[patent_app_type] => 1
[patent_app_number] => 9/317647
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/317647 | Diffusion barrier for increased mirror reflectivity in reflective solderable contacts on high power LED chip | May 23, 1999 | Issued |
Array
(
[id] => 4414457
[patent_doc_number] => 06229203
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[patent_title] => 'Semiconductor interconnect structure for high temperature applications'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/312537 | Semiconductor interconnect structure for high temperature applications | May 23, 1999 | Issued |
Array
(
[id] => 4356793
[patent_doc_number] => 06190944
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[patent_issue_date] => 2001-02-20
[patent_title] => 'Stacked package for semiconductor device and fabrication method thereof, and apparatus for making the stacked package'
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Array
(
[id] => 4084800
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[patent_title] => 'Method of forming a trench capacitor with a sacrificial silicon nitrate sidewall'
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Array
(
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Array
(
[id] => 4419535
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[patent_title] => 'Method to form MOSFET with an elevated source/drain for PMOSFET'
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Array
(
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Array
(
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Array
(
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Array
(
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[firstpage_image] =>[orig_patent_app_number] => 260001
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/260001 | Borderless vias | Mar 1, 1999 | Issued |