Search

Belur V. Keshavan

Examiner (ID: 12700)

Most Active Art Unit
2825
Art Unit(s)
2825, 2823
Total Applications
284
Issued Applications
267
Pending Applications
6
Abandoned Applications
11

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18105306 [patent_doc_number] => 11545200 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-03 [patent_title] => Data control circuit for increasing maximum and minimum tolerance values of skew between DQS signal and clock signal during write operation and associated memory device [patent_app_type] => utility [patent_app_number] => 17/498773 [patent_app_country] => US [patent_app_date] => 2021-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7095 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17498773 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/498773
Data control circuit for increasing maximum and minimum tolerance values of skew between DQS signal and clock signal during write operation and associated memory device Oct 11, 2021 Issued
Array ( [id] => 18688137 [patent_doc_number] => 11783880 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Operating method of memory device for extending synchronization of data clock signal, and operating method of electronic device including the same [patent_app_type] => utility [patent_app_number] => 17/496003 [patent_app_country] => US [patent_app_date] => 2021-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 16482 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17496003 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/496003
Operating method of memory device for extending synchronization of data clock signal, and operating method of electronic device including the same Oct 6, 2021 Issued
Array ( [id] => 18312165 [patent_doc_number] => 20230116065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => RE-PROGRAMMABLE INTEGRATED CIRCUIT ARCHITECTURE AND METHOD OF MANUFACTURE [patent_app_type] => utility [patent_app_number] => 17/488008 [patent_app_country] => US [patent_app_date] => 2021-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3157 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17488008 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/488008
Re-programmable integrated circuit architecture and method of manufacture Sep 27, 2021 Issued
Array ( [id] => 17956152 [patent_doc_number] => 11482265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Write leveling [patent_app_type] => utility [patent_app_number] => 17/486481 [patent_app_country] => US [patent_app_date] => 2021-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 14062 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17486481 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/486481
Write leveling Sep 26, 2021 Issued
Array ( [id] => 17346855 [patent_doc_number] => 20220013186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => DETERMINE SIGNAL AND NOISE CHARACTERISTICS CENTERED AT AN OPTIMIZED READ VOLTAGE [patent_app_type] => utility [patent_app_number] => 17/485096 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13563 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485096 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/485096
Determine signal and noise characteristics centered at an optimized read voltage Sep 23, 2021 Issued
Array ( [id] => 18464188 [patent_doc_number] => 11688481 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Semiconductor memory devices with diode-connected MOS [patent_app_type] => utility [patent_app_number] => 17/484730 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6224 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17484730 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/484730
Semiconductor memory devices with diode-connected MOS Sep 23, 2021 Issued
Array ( [id] => 18387085 [patent_doc_number] => 11657874 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Semiconductor storage device [patent_app_type] => utility [patent_app_number] => 17/480858 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8915 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480858 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/480858
Semiconductor storage device Sep 20, 2021 Issued
Array ( [id] => 19296162 [patent_doc_number] => 12035539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-09 [patent_title] => Magnetic memory and reading/writing method thereof [patent_app_type] => utility [patent_app_number] => 17/480357 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5680 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480357 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/480357
Magnetic memory and reading/writing method thereof Sep 20, 2021 Issued
Array ( [id] => 18827503 [patent_doc_number] => 11842792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => Interface circuit, data transmission circuit, and memory [patent_app_type] => utility [patent_app_number] => 17/479184 [patent_app_country] => US [patent_app_date] => 2021-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8374 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17479184 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/479184
Interface circuit, data transmission circuit, and memory Sep 19, 2021 Issued
Array ( [id] => 17917164 [patent_doc_number] => 20220319560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => MEMORY CIRCUIT, METHOD AND DEVICE FOR CONTROLLING PRE-CHARGING OF MEMORY [patent_app_type] => utility [patent_app_number] => 17/470895 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11053 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470895 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/470895
Memory circuit, method and device for controlling pre-charging of memory Sep 8, 2021 Issued
Array ( [id] => 18118988 [patent_doc_number] => 11550381 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Non-volatile memory system or sub-system [patent_app_type] => utility [patent_app_number] => 17/468155 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11849 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17468155 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/468155
Non-volatile memory system or sub-system Sep 6, 2021 Issued
Array ( [id] => 19031261 [patent_doc_number] => 11930636 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Transistor antifuse, and related devices, systems, and methods [patent_app_type] => utility [patent_app_number] => 17/468523 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 9340 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17468523 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/468523
Transistor antifuse, and related devices, systems, and methods Sep 6, 2021 Issued
Array ( [id] => 18721252 [patent_doc_number] => 11798604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Memory architecture having ranks with variable data widths [patent_app_type] => utility [patent_app_number] => 17/464407 [patent_app_country] => US [patent_app_date] => 2021-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4853 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17464407 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/464407
Memory architecture having ranks with variable data widths Aug 31, 2021 Issued
Array ( [id] => 17978441 [patent_doc_number] => 11495313 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-08 [patent_title] => Fail-safe IC production testing [patent_app_type] => utility [patent_app_number] => 17/463631 [patent_app_country] => US [patent_app_date] => 2021-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5267 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17463631 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/463631
Fail-safe IC production testing Aug 31, 2021 Issued
Array ( [id] => 18105316 [patent_doc_number] => 11545210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Apparatuses, systems, and methods for fuse array based device identification [patent_app_type] => utility [patent_app_number] => 17/446569 [patent_app_country] => US [patent_app_date] => 2021-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6661 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17446569 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/446569
Apparatuses, systems, and methods for fuse array based device identification Aug 30, 2021 Issued
Array ( [id] => 18431449 [patent_doc_number] => 11676676 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Merged bit lines for high density memory array [patent_app_type] => utility [patent_app_number] => 17/461898 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7106 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461898 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/461898
Merged bit lines for high density memory array Aug 29, 2021 Issued
Array ( [id] => 17886130 [patent_doc_number] => 20220301607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => MEMORY SYSTEM AND DELAY CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 17/459536 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11713 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17459536 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/459536
Memory system and delay control method Aug 26, 2021 Issued
Array ( [id] => 18219326 [patent_doc_number] => 11594272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-28 [patent_title] => Sensing a memory cell [patent_app_type] => utility [patent_app_number] => 17/409608 [patent_app_country] => US [patent_app_date] => 2021-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 16657 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17409608 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/409608
Sensing a memory cell Aug 22, 2021 Issued
Array ( [id] => 17645014 [patent_doc_number] => 20220172753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => MEMORY DEVICE, MEMORY SYSTEM, AND OPERATING METHOD OF MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/409064 [patent_app_country] => US [patent_app_date] => 2021-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16171 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17409064 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/409064
Memory device, memory system, and operating method of memory system Aug 22, 2021 Issued
Array ( [id] => 18357661 [patent_doc_number] => 11646067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-09 [patent_title] => Data storage device and operating method thereof [patent_app_type] => utility [patent_app_number] => 17/407557 [patent_app_country] => US [patent_app_date] => 2021-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 7612 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17407557 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/407557
Data storage device and operating method thereof Aug 19, 2021 Issued
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